EPM3512AQC208-7N vs EPM3512AQC208-3N Perbandingan

Perbandingan bersamaan detil EPM3512AQC208-7N dari Altera dan EPM3512AQC208-3N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ Waktu Beli Terakhir

Perbandingan Spesifikasi

Parameter Umum EPM3512AQC208-7N EPM3512AQC208-3N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Waktu Pembelian Terakhir Obsolete
Family MAX 3000A MAX 3000A
Logic Capacity 512 macrocells, 10,000 usable gates —
Logic Array Blocks (LABs) 32 16
Macrocells per LAB 16 32
User I/Os 172 —
Propagation Delay (tPD) 7.5 ns —
Maximum Frequency (fCNT) 116.3 MHz —
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
I/O Bank Count 4 (MultiVolt) —
Supported I/O Standards 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS —
Process Technology 0.30 µm CMOS EEPROM —
Configuration Non-volatile EEPROM, in-system programmable (ISP) —
JTAG Interface IEEE 1149.1 BST + IEEE 1532 ISP —
Paket 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) PQFP-208
Suhu Kerja 0 °C to +70 °C (commercial) 0C to +70C (commercial)
Status RoHS Compliant [DATA_NEEDED: not stated in retrieved snippets]
Speed Grade -7 —
Macrocells — 512
User I/O Pins — 172
Pin-to-Pin Logic Delay — 3 ns (speed grade -3)
Global Clock Setup Time — [DATA_NEEDED: actual tSU at 3 ns grade]
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant)
Tipe Mounting — Surface Mount
Programming Technology — EEPROM (non-volatile, in-system programmable)
JTAG / Boundary Scan — IEEE 1149.1 compliant
ISP Compliance — IEEE Std. 1532
Lead-Free / Halogen-Free — [DATA_NEEDED]

Spek dan Sumber

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