EPM5064LC-2 vs EPM5064JC1 Perbandingan
Perbandingan bersamaan detil EPM5064LC-2 dari Altera dan EPM5064JC1 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5064LC-2 | EPM5064JC1 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Logic Elements per LAB | 16 | — |
| Number of Inputs | 36 (7 dedicated + 28 I/O) | — |
| Number of I/O Pins | 28 | — |
| Number of Flip-Flops | 28 | — |
| Propagation Delay (tPD) | 45 ns | — |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) | CMOS |
| Programmable Polarity | Yes | — |
| Programmable Output Enable | Yes, per macrocell | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Suhu Kerja | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] | — |
| Paket | PLCC-44 (J-Lead, plastic) | 44-pin PLCC (J-Lead) |
| Tipe Mounting | Surface Mount | — |
| Status RoHS | [DATA_NEEDED: not specified in source] | unknown |
| Programming Method | Altera byte-wide / JTAG programmer | — |
| Family | — | MAX 5000 |
| Device Type | — | CPLD / EPLD (Erasable PLD) |
| Usable Gates | — | 1.25K |
| Maximum Operating Frequency (fCNT) | — | 62.5 MHz |
| External Clock Input (max) | — | 50 MHz |
| I/O Pins | — | 28 |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 36 (28 I/O + 7 dedicated + 1 clock) |
| Operating Voltage (VCC) | — | 5 V |
| Program Type | — | EPROM (one-time programmable, UV-erasable) |
| Operating Temperature (JC suffix) | — | 0°C to +70°C (commercial) |
| Supply Current (ICC) | — | [DATA_NEEDED: ICC maximum] |
| Lead-Free Status | — | unknown |