EPM7128AET1100-7 vs EPM7128ATC100-10 Perbandingan
Perbandingan bersamaan detil EPM7128AET1100-7 dari Intel dan EPM7128ATC100-10 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EPM7128AET1100-7 - 128-Macrocell MAX 7000A CPLD | Intel
EPM7128AET1100-7 ⚠ Waktu Beli TerakhirAltera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoletePerbandingan Spesifikasi
| Parameter Umum | EPM7128AET1100-7 | EPM7128ATC100-10 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Obsolete |
| Family | MAX 7000A (MAX 7000AE) | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2.5K |
| User I/O Pins | 84 | 68 |
| Logic Elements / LABs | [DATA_NEEDED: LAB count for 7128A] | — |
| Speed Grade | -7 (5 ns pin-to-pin) | -10 (10 ns) |
| Supply Voltage VCC | 5.0 V (typical) | — |
| I/O Voltage Tolerance | 3.3 V / 5.0 V | — |
| Suhu Kerja | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Paket | TQFP-100 | 100-pin TQFP (TC100) |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Programming Interface | IEEE 1149.1 JTAG / ByteBlaster | — |
| Tipe Mounting | Surface Mount | Surface Mount |
| Level MSL | 3 (168 hours, per JEDEC J-STD-020) | — |
| Status RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes | — |
| Process Technology | CMOS, EEPROM-based | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX) |
| Logic Array Blocks (LABs) | — | 4 |
| Pin-to-Pin Logic Delay | — | 4.5 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Core Supply Voltage | — | 3.3 V |
| I/O Logic Level Support | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Program Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |