EPM9320ARI208-10N vs EPM9560ARI208-10N Perbandingan
Perbandingan bersamaan detil EPM9320ARI208-10N dari Altera dan EPM9560ARI208-10N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteAltera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N ObsoletePerbandingan Spesifikasi
| Parameter Umum | EPM9320ARI208-10N | EPM9560ARI208-10N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 12,000 |
| Macrocells | 320 | 560 |
| Logic Array Blocks (LABs) | 20 | 35 |
| Maximum Operating Frequency | 144.9 MHz | — |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | — |
| Tegangan Pemuat | 4.5 V to 5.5 V | 5.0 V |
| Suhu Kerja | -40 C to +85 C (industrial) | 0 C to 70 C (Commercial) |
| Paket | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (Plastic) |
| Tipe Mounting | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system (ISP) via IEEE 1149.1 JTAG | — |
| Global Dedicated Inputs | 16 | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | — |
| Status RoHS | unknown | — |
| Maximum User I/O Pins | — | 212 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD1) | — | 10 ns |
| Clock-to-Output (tCO) | — | 4.5 ns |
| Setup Time (tSU) | — | 3.0 ns |
| Maximum Counter Frequency (fCNT) | — | 144.9 MHz |
| Logic Family | — | CMOS EEPROM |
| Programming Interface | — | JTAG (IEEE 1149.1) - In-System Programmable |