Analog IMC advances low-power AI inference at 12nm and in CMOS

Reported by EE News Europe on November 10, 2026. Summarized and analyzed by XAIPART Editorial.

What happened

Analog In-Memory Compute performs selected operations within memory, reducing the movement of data between processing and memory units; the article identifies lower latency and energy use as its main objectives for AI inference.^S1 Work has continued for at least a decade using resistive, phase-change and capacitive elements, while AI workloads have renewed interest because crossbar arrays can hold neural-network weights.^S1

Weebit Nano has released ReRAM evaluation boards built around a 32 x 32 crossbar array, including a quick-start setup with an FPGA, ADCs, an AMD Zync Z-board and ten packaged die.^S1 Its research package exposes individual ReRAM cells for device characterization and programming development, while the company is pursuing a licensing model for controllers, CPUs, GPUs and SoCs.^S1

TetraMem has taped out the MLX300, a 12nm analog IMC SoC for audio, vision and small language models that can hold up to 64 million INT4 parameters without external DRAM for model weights.^S1 The chip targets more than 50–80 TOPS/W and follows the 22nm MLX200 and MLX200M; the earlier MLX200 integrates multi-level RRAM arrays with mixed-signal engines, and its evaluation kits were expected shortly.^S1

Other approaches include INTERA’s fully CMOS-based Programmable Current Pulse Cell, EnCharge AI’s capacitor-based EN100 accelerator and IBM’s work on 3D analog memory for mixture-of-experts models.^S1 HP and Hong Kong University have also developed a fault-tolerant memristor approach that uses adjustable submatrices to bypass failed devices.^S1

Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.