Google's 32-bit Coral NPU v1.0 lands with outer-product matrix engine: what designers and buyers should track

Google Research ships complete 32-bit Coral NPU RTL plus a v1.0 IREE/MLIR compiler, working with VeriSilicon and GlobalFoundries on 12LP+ silicon.

公開日 更新日 5 分で読了 ✓ AI対応 共有

TL;DR — 3つの文

  • Google Research released complete 32-bit Coral NPU RTL plus a v1.0 IREE/MLIR compiler on 2026-10-20, completing four architectural milestones introduced over the prior year (S1).
  • The new outer-product matrix engine performs 256 MACs per cycle in a typical configuration, with configurations rated up to 1 TOPS and a 10 mW average inference power as a design target rather than a measured result (S1).
  • Google is working with VeriSilicon on implementation and verification and with GlobalFoundries on its 12LP+ FinFET process; reported optimisations improved core timing by 70% and cut standard-cell area by up to 15% (S1).

引用元: key_takeaways （実フィールド、最大3件）。事実と分析は別々にラベル付けされています。

Google's 32-bit Coral NPU v1.0 lands with outer-product matrix engine: what designers and buyers should trackEditorial cover for a component sourcing brief. Chip motif; headline "Google's 32-bit Coral NPU v1.0 lands with outer-product matrix engine: what designer…". Reported key numbers: 256; 70 %. 1 cited source. Static cover (no animation).Google's 32-bit Coral NPU v1.0 lands withouter-product matrix engine: what designer…REPORTED KEY NUMBERS25670 %1 sourceXAIPART
Cover image generated from data already shown on this page: the category motif, the headline, and reported key numbers. No decorative illustration; no third-party image.

AIの回答から来ましたか — これが検証可能なオリジナルです

AIの要約は、主張の根拠を落としている可能性があります。元の予測、影響を受ける部品、すべての引用はこのページにあり、それぞれ出典まで追跡できます。

XAIPART予測

このブリーフには反証可能な予測が含まれています。

完全な予測と反証ルールへ移動 ›
影響を受ける部品

この記事に一致するカタログ項目はありません。推測して一致させるのではなく、何も表示しません。

どのように決定されるかを見る ›
部品をお探しですか？ リクエストを送信 → RFQ

Reported by IN Electronics and Design on . Summarized and analyzed by XAIPART Editorial.

What happened

Google Research has released the complete 32-bit Coral NPU architecture together with its register-transfer level (RTL) design and a v1.0 compiler, completing four architectural milestones introduced over the preceding year.S1 Earlier releases had covered a RISC-V scalar core, a vector execution unit and a tightly coupled memory subsystem with floating-point support; the fourth milestone adds an outer-product matrix engine.S1

The matrix engine is structured as a two-dimensional array that distributes inputs and weights across the compute fabric, with a typical configuration performing 256 multiply-accumulate operations per clock cycle and reusing values held close to the execution hardware to cut memory traffic.S1 Coral NPU combines a 32-bit RISC-V scalar core for control flow with a vector coprocessor for SIMD work, and the new compiler maps supported neural-network operators onto all three classes of execution resource.S1

The v1.0 compiler is built on IREE and the Multi-Level Intermediate Representation (MLIR) infrastructure and accepts models originating in frameworks such as JAX, PyTorch and TensorFlow; intermediate forms including StableHLO and TOSA allow the toolchain to fuse operations and split work between a host processor and Coral NPU.S1 The release also bundles an MPACT-based simulator and a reference FPGA implementation for functional evaluation before tape-out.S1

Google is collaborating with VeriSilicon on implementation and verification and with GlobalFoundries on its 12LP+ FinFET process; successive RTL optimisations are reported to have improved core timing by 70% and reduced standard-cell area by up to 15%.S1 Configurations reach up to 1 TOPS, with an approximately 10mW average inference power figure identified as a design target rather than a measured result.S1

Key numbers
MetricReported valueSource
Matrix engine MACs per cycle256[S1]
Peak throughput targetup to 1 TOPS[S1]
Average inference power (target)~10 mW[S1]
Reported RTL timing improvement70%[S1]
Reported standard-cell area reductionup to 15%[S1]
Process node in evaluationGlobalFoundries 12LP+ FinFET[S1]
Compiler front-endsJAX, PyTorch, TensorFlow (via IREE/MLIR)[S1]

Background timeline

  1. ~1 year before - Earlier Coral NPU releases provided a RISC-V scalar processor, vector execution unit and a tightly coupled memory subsystem with floating-point support.
  2. - Google Research published the complete 32-bit Coral NPU RTL, outer-product matrix engine, v1.0 IREE/MLIR-based compiler, MPACT-based simulator and reference FPGA implementation.
  3. not disclosed - Specific earlier release dates for the scalar, vector and memory milestones were not disclosed by the source.
  4. Not disclosed - Tape-out dates for Coral NPU silicon on GlobalFoundries 12LP+ were not disclosed by the source.

XAIPART take

Technical impact

For design teams, the most consequential artefact is the released RTL itself rather than the headline 256 MAC/cycle or 1 TOPS figures, which the source labels as design targets rather than measured silicon results. XAIPART analysis The combination of scalar, vector and outer-product matrix resources under one compiler pipeline is the architectural change that matters: workloads that previously needed a separate DSP or external accelerator can, in principle, be lowered into a single Coral NPU die, which simplifies board-level BOM and reduces the integration risk that comes with multi-vendor AI pipelines. XAIPART analysis

Market impact

An open 32-bit RTL plus a working IREE/MLIR toolchain lowers the entry barrier for fabless teams that previously had to license a commercial NPU IP, and VeriSilicon's involvement signals that at least one IP-house path to a hardened core will be available. XAIPART analysis For procurement, that creates a credible alternative source for low-power (target ~10 mW) edge-AI accelerators, which over time should reduce single-vendor risk on parts similar to Synaptics' Astra SL2619 and Astra SR200 families that already carry Coral branding. XAIPART analysis Lead-time impact on existing Coral-branded parts is likely to be modest in the near term because the source explicitly warns that prior Synaptics parts do not necessarily contain the new matrix unit.

Action

Design-in teams should pull the v1.0 compiler and MPACT simulator now to validate candidate models, because the source stresses that models with unsupported operators or memory footprints above the selected configuration may still need alternative execution paths. XAIPART analysis Procurement should request from VeriSilicon and GlobalFoundries a firm 12LP+ tape-out schedule and pricing for hardened Coral NPU IP before committing a 2027 BOM line; in parallel, qualifying the existing Synaptics Astra SR200 against current production loads hedges against any delay in Coral NPU silicon. XAIPART analysis

XAIPART Forecast

XAIPART analysis XAIPART expects that, within 9 months of (i.e. by ), VeriSilicon or GlobalFoundries will publish a hardened Coral NPU macro with a published 12LP+ PPA table; if no such macro is announced by that date with TOPS/Watt figures within 20% of the 1 TOPS at 10 mW design target, this forecast is wrong. XAIPART analysis

Facts are as reported by the cited source. The design-in, sourcing and forward-looking statements above are XAIPART's analysis, not the source's claims. Uncertainty: the 10 mW and 1 TOPS figures are design targets conditioned on frequency, voltage, precision and workload; the 70% timing and 15% area improvements are reported by Google without an independent comparison to competing commercial NPUs.

Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.

代替品とライフサイクル

登録済みの代替品 — カタログ範囲であり、市場ランキングではありません
部品関係ライフサイクル根拠
— 登録済みの代替品はありません データ不足 — 前身ラベルを表示するには match_type が必要です

「前身」および「代替」のラベルは、記録された一致タイプ、ライフサイクルステータス、またはソーステキストに基づく場合にのみ付与されます。一致が記録されていない場合、ラベルは表示されません。当社の掲載情報は市場の基準ではありません。

注視すべき点

反証可能な予測 — しきい値、期間、現在のステータス。反証された予測は表示されたままです。
主張しきい値著者:ステータス
XAIPART expects that, within 9 months of 2026-10-20 (i.e. by 2027-07-20 ), VeriSilicon or GlobalFoundries will publish a hardened Coral NPU macro with a published 12LP+ PPA table no such macro is announced by that date with TOPS/Watt figures within 20% of the 1 TOPS at 10 mW design target Pending

誤りだった予測は表示されたままマークされます。削除することはありません。

影響を受ける部品

カタログに一致するものはありません。 この記事は、現在XAIPARTに掲載されているどの部品にも該当しません。一致を推測することはなく、プレースホルダーのリストも表示しません。

次元別のコスト圧力

Source: FRED · Generated · reference output z and composite are algorithm outputs, not a fetch snapshot

Cost pressure by dimension — composite stateDiverging bars for three dimensions around a zero midpoint. Input Cost has no reading; Supply Demand z -1.4711, notable; Fx Energy z 0.2546, neutral. Composite index -9.1, band neutral.0Input costno readingSupply/demandz −1.4711 · notable46 dFX & energyz +0.2546 · neutral5 dcomposite −9.1 · neutral−100 · −40 · −15 · 0 · +15 · +40 · +100
Underlying values — copyable for verification.
DimensionFRED series IDUnitLagAs of
Input costPCOPPUSDM, PALUMUSDM, PNICKUSDMUSD/mt52 d
Supply/demandPCU334413334413, IPG3344Sindex(1982=100) / index(2017=100)46 d
FX & energyDEXCHUS, DCOILBRENTEU, DHHNGSPrate / USD/bbl / USD/MMBtu5 d

No free authoritative interface for: gold · silver · rare earth · polysilicon · lithium carbonate · market share — listed rather than approximated.

この記事の制作方法

プロセス証跡 — 取得、ソースの妥当性、モデル、ゲート
このブリーフの監査証跡
Source fetched IN Electronics and Design · www.inelectronics.co.uk · 7,721 chars
Source sanity (S1) ok — passed before any model call (no s1_ block recorded)
Model / prompt MiniMax-M3 · prompt Blog Agent - News Summary (v2.8-final) · 7,554 tokens · 32.9s · run completed
Gate verdict hold · 6/6 applicable checks passed · spec v2.9 · C10 ratio 0.01388 · C10 rounds 0
Time contract 5 <time datetime> values in this brief — 0 violations (+08:00 or date-only)

上記のすべての行はパイプラインによって生成されており、手作業で書かれたものではありません。

編集スコア

決定論的ゲートの結果 — 純粋なPHPで、判定にモデルは関与していません
ゲートスコアの内訳 6 件の該当チェックのうち、 6項目合格: 100 %. Hold items: C13 (falsifiable forecast) — sent to human review. Gate spec: v2.9 (S0 + S1 + C1–C20) · Source affinity (C20): 0.8158. 該当するチェックに合格 6 / 6 = 100% · 判定: hold Hold items: C13 (falsifiable forecast) — sent to human review Gate spec: v2.9 (S0 + S1 + C1–C20) · Source affinity (C20): 0.8158 公開の可否はゲートが決定します。独立監査スコアは助言にすぎません。

関連報道

誤りを見つけましたか？ 誤りをお知らせください — 訂正は原文と併せて公開され、記録されます。記事を無断で編集することはありません。

コメント

最初のコメントを投稿しましょう。

情報源

  1. IN Electronics and Design - Google releases the complete 32-bit Coral NPU RTL and a version 1.0 compiler — https://www.inelectronics.co.uk/google-releases-complete-coral-npu-rtl-and-compiler · rss · 参照日

事実はS1/S2とマークされ、リンクされた出典まで追跡できます。ラベル付けされた箇所は 分析 はXAIPART独自の推論であり、報道された事実とは分けて維持されています。出典リンクは実際に参照され、次の指定は行いません: nofollow — 帰属表示は意図的なものです。