PIC24FJ128GB202-E/MM
PIC24FJ128GB202-E/MM - 16-bit XLP MCU, 128KB Flash, USB, Crypto | Microchip
The Microchip Technology PIC24FJ128GB202-E/MM is a 16-bit microcontroller from the PIC24F eXtreme Low Power (XLP) family, integrating a hardware crypto engine, USB 2.0 full-speed device/host/OTG, and 128 KB of self-programmable Flash in a 28-pin 6x6 mm QFN-S package. It operates at up to 32 MHz MIPS core clock with 8 KB SRAM and is engineered for ultra-low-power embedded designs where both cryptographic acceleration and USB connectivity are required on the same die.
A 16-bit microcontroller (MCU) is a programmable processor whose arithmetic logic unit, registers, and internal bus are 16 bits wide, balancing the 8-bit MCU's code density with the 32-bit MCU's throughput. PIC24F devices sit in Microchip's mid-range 16-bit portfolio between 8-bit PIC16/PIC18 parts and 32-bit PIC32 parts, sharing the same MPLAB X toolchain, XC16 compiler, and Harmony framework as the wider dsPIC/PIC24/PIC32 family. The "FJ" prefix denotes Flash program memory with the XLP sleep architecture, "GB" denotes integrated USB plus crypto, and "202" identifies the 28-pin pinout with 128 KB Flash.
Key features of the PIC24FJ128GB202-E/MM include: 128 KB (43K x 24) Flash program memory with self-programming and live update, 8 KB SRAM, integrated hardware crypto engine supporting AES, DES, 3DES, SHA-1/SHA-256 and RNG, USB 2.0 FS device/host/OTG with on-chip transceiver and PHY, two I2C, two SPI, up to two UART, two comparators, a 10-bit ADC with up to 9 channels, 5-bit DAC, three 16-bit timers, RTCC with calendar, and a chargeable nanoWatt XLP deep-sleep mode drawing sub-µA currents. The on-chip 32 kHz crystal-less USB PLL and the CTMU touch-sensing peripheral reduce external BOM cost. The QFN-S (6x6 mm) package provides a thermally efficient exposed paddle suitable for hand-held and USB-powered devices.
The PIC24FJ128GB202 architecture pairs a modified Harvard CPU with a 24-bit instruction word for compact code density, a single-cycle hardware multiplier, and a deterministic interrupt controller. The integrated crypto block offloads AES-128/192/256 and SHA operations from the core, so secure firmware updates, signed firmware boot, and TLS-style handshakes run in milliseconds rather than tens of milliseconds. The USB block shares DMA with the rest of the peripherals and supports device, host, and OTG roles, eliminating the need for an external PHY in most token, HID, CDC, and Mass Storage designs.
Typical applications for this part include USB smart-card and authentication tokens, secure medical data loggers with USB charging/docking, encrypted industrial sensor hubs that stream over USB, low-power IoT edge nodes that need both USB firmware update and secure boot, e-metering and tamper-resistant metering devices, and battery-powered consumer accessories such as USB-C hearables and wearables. Designers choose the "E" temperature grade (-40C to +125C) for industrial and extended-temperature environments.
A practical design tip: route the USB D+/D- pair as a 90-ohm differential microstrip with ground stitching vias on both sides, keep the 27-ohm series resistors within 4 mm of the IC, and place the VBUS bulk capacitor as close as possible to the VBUS pin to pass USB compliance and ESD tests. The QFN exposed paddle must be soldered to a continuous ground copper pour with thermal vias to meet the 1.5 W dissipation budget in enclosed industrial enclosures.
This page synthesizes distributor pricing, same-package Microchip alternatives, and practical USB/crypto design notes not found in a single datasheet table.
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