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PN7161B1HN-C100Y - NFC Controller with NCI Interface | NXP
The NXP Semiconductors PN7161B1HN-C100Y is an EMV L1 compliant NFC controller with NCI interface, supporting EMV and NFC Forum applications plus Apple Enhanced Contactless Polling (ECP). It operates at 13.56 MHz and integrates all RF analog front-end, protocol stack handling, and host interface logic in a 40-pin HVQFN (HVQFN-40) exposed-pad package. The device supports a 1.65 V to 1.95 V or 3.0 V to 3.6 V supply range with SPI host interface. What is an NFC controller? An NFC (Near Field Communication) controller is a specialized mixed-signal IC that handles the 13.56 MHz RF physical layer and the NFCIP-1, NFCIP-2, ISO 14443, ISO 15693, FeliCa, and MIFARE protocol stacks, exposing a standardized host interface (NCI, NCI 2.0) to the application processor. In the system hierarchy, an NFC controller sits between the RF antenna and the host CPU and belongs to the broader category of short-range wireless ICs within RF & wireless semiconductor products. Key features include integrated RF front-end with automatic antenna tuning support, full NFC Forum tag type and peer-to-peer mode support, EMVCo L1 and L2 stack offload, dynamic load modulation for Apple ECP, low-power standby modes, and an integrated LDO for the RF section. The PN7161 builds on the PN7160 by adding Apple ECP enablement after formal authorization, while keeping the same VQFN-40 footprint and pinout. The device architecture combines an ARM Cortex-M0 core for firmware execution with hardware accelerators for framing, crypto, and EMVCo polling loops. A high-efficiency RF transmitter uses a single-ended output driving an external EMC filter and matching network, while a pair of differential Rx inputs accept the tag/NFC device response. An integrated temperature sensor and battery-friendly deep-sleep modes reduce idle consumption below typical NFC reader IC benchmarks. Typical applications include NFC payment terminals (POS), mobile point-of-sale accessories, EMV contactless readers, access control and ticketing readers, NFC-enabled IoT gateways, and automotive digital key / wireless charging authentication modules. The wide host-side voltage range also makes it suitable for direct connection to 1.8 V application processors. When designing with this device, allocate at least 4 layers of the PCB to the RF section and follow the NXP antenna design guide for the matching network and EMC low-pass filter. A stable host supply and a clean reset sequence are required during firmware download and after EMV stack updates. This page consolidates distributor pricing, drop-in NXP same-family alternatives, and application-specific design notes that complement the manufacturer datasheet and the NXP NFC forum reference designs.
PN7220 - 2W High-Power NFC Controller NCI 2.2 | NXP Semiconductors
The NXP Semiconductors PN7220 is a high-power NFC controller with NCI interface, delivering more than 2.0 W RF output power with high receiver sensitivity in a 64-ball VFBGA package, operating from a 2.4 V to 5.5 V supply with I2C, SPI, and USB host interfaces at 13.56 MHz. An NFC controller is a dedicated frontend IC that manages the contactless radio link between a host processor (smartphone, payment terminal, embedded reader) and NFC cards, tags, or phones. It sits within the RFID/contactless hierarchy: NFC controller -> NFC frontend IC -> RFID transceiver -> wireless connectivity IC, and implements the NFC Forum NCI (NFC Controller Interface) standard so the host stack stays portable. Key differentiating features include NCI 2.2 compliance, more than 2.0 W RF output power for robust field generation in electromagnetically difficult environments, integrated power management that reduces external BOM count, and secure mode switching for payment-grade operation. The part supports EMVCo 3.1 and NFC Forum analog/digital testing targets, making certification faster. Architecturally, the PN7220 integrates the RF analog front end, a contactless protocol engine (ISO 14443A/B, ISO 15693, MIFARE, FeliCa), an embedded firmware core, and voltage regulation on a single die. High receiver sensitivity extends read range with small antennas, while the strong transmit field improves performance near metal or with tightly coupled antenna matching networks. Typical applications include Android-based EMVCo payment terminals, vending machines with contactless payment, NFC Forum readers, industrial access control readers, and point-of-sale peripherals. Design consideration: because output power exceeds 2 W, PCB antenna matching and thermal copper area under the VFBGA must follow the NXP hardware design guidance to stay within EMVCo field tolerances. This page adds value beyond the datasheet by synthesizing distributor availability, drop-in alternative analysis (PN7221), and practical design notes for payment and reader designs.
PN7642 - NFC Reader IC with Cortex-M33 MCU & Security | NXP
The NXP Semiconductors PN7642 is a highly integrated NFC open controller that combines a high-performance NFC reader, a low-power Arm Cortex-M33 microcontroller with 180 kB of programmable flash memory, and a Common Criteria EAL6+ certified secure element, supplied in a BGA form factor (PN7642EV orderable variants). An NFC reader controller is a single-chip integration of an RF analog front end (for 13.56 MHz contactless communication), protocol firmware, and a host-processing MCU. Within the system hierarchy, it belongs to the RF & Wireless > NFC/RFID reader family: antenna driver -> NFC frontend -> NFC controller with MCU (PN7462, PN7642). By merging reader, MCU, and secure element, the PN7642 replaces the need for an extra discrete MCU and a dedicated Secure Element in the bill of materials, reducing board area and BOM cost in payment and access-control designs. Key features include the integrated Common Criteria EAL6+ certified secure element, EMVCo certification for contactless payments, support for ISO 14443 (Type A and Type B) and NFC Forum protocols, and the Arm Cortex-M33 core with 180 kB of user-programmable flash. GPIO resources include multi-function pins such as GPIO2 (PWM2 capability) and GPIO3 (PWM3 capability); when ULPCD (Ultra-Low-Power Card Detection) is used, GPIO3 must be dedicated to aborting the ULPCD function and cannot be allocated to other roles. Technically, the PN7642 pairs a high-performance NFC frontend with a customizable MCU subsystem, enabling customer firmware to implement application logic, key management, and cryptographic operations on-chip. The security toolbox addresses secure key storage, a primary requirement for payment terminals and secure access readers, and the part is supplied in a compact BGA package suitable for space-constrained embedded designs. Typical applications include EMVCo contactless payment terminals, secure access-control and identity readers, and NFC-enabled IoT devices that require both contactless connectivity and embedded security without external components. Design consideration: firmware architecture must account for pin multiplexing constraints such as GPIO3 contention with ULPCD, and designers should consult NXP design-in documents beyond the product data sheet, since detailed design-in information is distributed separately by NXP. This page synthesizes verified distributor pricing, drop-in alternative analysis, and practical design notes not found in the manufacturer datasheet.
PN7642EV - NFC Reader + Arm Cortex-M33 MCU 64-VFBGA | NXP
The NXP Semiconductors PN7642EV is a highly integrated NFC open controller that combines a high-performance 13.56 MHz NFC reader, a low-power Arm Cortex-M33 microcontroller with 180 kB of programmable flash memory, and a security subsystem optimized for secure key storage and cryptography, housed in a 64-ball VFBGA package. An NFC controller IC is a single-chip device that manages contactless communication according to proximity-coupling standards such as ISO 14443-A/B, ISO 15693, FeliCa, and NFC Forum protocols. Within the system hierarchy, it sits between the RF antenna front end and the host application layer, replacing the classic three-chip combination of a dedicated NFC reader IC, a general-purpose MCU, and a discrete Secure Element with one integrated solution. Key features include the integrated Arm Cortex-M33 core running application firmware from 180 kB of on-chip flash, full reader/writer (PCD) support for ISO14443-3/4 A/B, ISO15693 / ISO18000-3 mode 1, FeliCa, ISO18000-3 mode 3, and MIFARE, plus card-emulation (PICC, ISO14443-4A) capability, and up to 21 general-purpose I/Os with PWM functions on GPIO2 and GPIO3. The security toolbox provides secure key storage and cryptographic acceleration, allowing the PN7642 to replace an external secure element in access-control and authentication designs. Host connectivity is flexible via I2C, SPI, UART, or USB, and the device ships pre-initialized with firmware by version code (C100 = firmware 01.00, C101 = firmware 02.00 with pinless-download mode enabled by default, C102 = firmware 03.00). Typical applications include door-access readers, industrial NFC configuration ports, point-of-sale peripherals, and embedded secure-provisioning systems. Design consideration: the PN7642EV (VFBGA) and PN7462AUHN (QFN) are not footprint-compatible despite functional overlap, so package selection must be fixed before PCB layout. This page synthesizes distributor pricing, firmware-variant selection guidance, and practical design notes not found in the manufacturer datasheet.
PN7642EV-C101Y - NFC Controller, Cortex-M33, 64-VFBGA | NXP
The NXP Semiconductors PN7642EV-C101Y is a highly integrated NFC open controller combining a high-performance 13.56 MHz NFC reader, a low-power Arm Cortex-M33 microcontroller with 180 kB of programmable flash memory, and a security subsystem optimized for secure key storage and cryptography, housed in a 64-ball VFBGA package (4.5 mm x 4.5 mm) operating from 2.4 V to 5.5 V. An NFC controller is a mixed-signal system-on-chip that manages contactless communication in the 13.56 MHz ISM band, implementing reader/writer (PCD), card emulation (PICC), and peer-to-peer functions defined by NFC Forum and ISO protocols. In the system hierarchy, it sits between the analog RF front end and the host application layer, and the PN7642 replaces the need for a separate external MCU and a dedicated secure element in a single chip. Key features include support for ISO 14443-3/4-A, ISO 14443-3/4-B, ISO 15693, ISO 18000-3 mode 1 and mode 3 / FeliCa, and MIFARE, plus card emulation per ISO 14443-4A. Host connectivity is highly flexible with I2C, SPI, UART, and USB 2.0 interfaces. Up to 21 general-purpose I/Os with PWM capability enable direct control of LEDs, buzzers, and power sequencing in terminal designs without additional discretes. The integrated security toolbox provides secure key storage and cryptographic acceleration, allowing the PN7642 to handle authentication, key diversification, and encrypted sessions locally. The Arm Cortex-M33 core delivers sufficient headroom for custom application firmware while the 180 kB flash supports field customization. The C101 firmware suffix denotes firmware version 02.00 with pinless-download mode enabled by default, per the NXP PN7642 product data sheet. Typical applications include NFC readers for point-of-sale terminals, access control readers, industrial and building automation nodes, and smart-home or IoT devices requiring contactless provisioning. Design consideration: with a maximum supply current of up to 400 mA during RF field-on transients, the 2.4 V to 5.5 V supply rail and PCB power delivery must be sized accordingly, and the antenna matching network layout should follow the NXP PN7642 reference design. This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
PN7642EV/C100K - NFC Controller with Cortex-M33 MCU | NXP
The NXP Semiconductors PN7642EV/C100K is a high-performance NFC open controller that integrates an Arm Cortex-M33 microcontroller, a full NFC reader front end for 13.56 MHz contactless communication, and a hardware security subsystem in a single 64-ball VFBGA package. It operates from a 1.8 V to 3.5 V supply and supports ISO 14443-A, ISO 14443-3/4-B, ISO 15693, ISO 18092 (NFCIP-1), ISO 18000-3, MIFARE and FeliCa protocols, with host interfaces including I2C, SPI, UART and USB. An NFC controller is a specialized mixed-signal integrated circuit that modulates and demodulates 13.56 MHz RF signals and executes contactless protocol stacks. Within the system hierarchy, the PN7642 sits above discrete NFC front ends: by combining the analog NFC front end, a general-purpose MCU and a secure element on one die, it functions as a complete NFC reader system-on-chip within the connectivity layer of a terminal design. Key differentiating features include 180 kB of programmable flash memory (256 kB total memory per distributor listings), an integrated security toolbox optimized for secure key storage and cryptography, and low-power operation suited to battery-powered readers. The single-chip architecture removes the need for a separate host MCU and a discrete secure element, reducing bill-of-materials count and board area. Technically, the PN7642 combines NXP's proven NFC RF front end with an Arm Cortex-M33 CPU core, providing developer-customizable firmware on the C100 firmware version (01.00). GPIO pins with PWM capability (for example GPIO2/GPIO3 on balls E7 and D7) allow direct control of LEDs, buzzers and power switches. The datasheet also documents firmware variants C101 (02.00, pinless-download mode) and C102 (03.00) for field-upgradeable deployments. Typical applications include point-of-sale payment terminals, access-control readers, battery-powered smart locks, and industrial handheld readers. The security subsystem makes it particularly suited to payment and authentication use cases requiring cryptographic key protection. A key design consideration is the 64-ball VFBGA package: ball-grid mounting requires controlled reflow profiles and is not hand-solderable, so panel design and rework capability should be confirmed before layout. Antenna matching network design should follow the NXP PN7642 antenna design guidance for 13.56 MHz EMC performance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
PR5331C3HN - 13.56MHz USB NFC Reader IC | NXP | 40-VFQFN
The NXP PR5331C3HN is a highly integrated 13.56 MHz contactless NFC reader/writer transceiver with USB interface, housed in a 40-VFQFN Exposed Pad package. It supports FeliCa, ISO 14443 A/B, and MIFARE protocols via I2C and UART, operates from 2.5V to 3.6V, and delivers plug-and-play NFC functionality for embedded reader designs. According to the NXP product page, the part integrates an internal microcontroller that runs a dedicated ROM code to handle the full RF protocol stack, offloading the host processor from real-time NFC tasks. What is an NFC reader IC? An NFC (Near Field Communication) reader IC, also called a contactless front-end or HF RFID transceiver, is a semiconductor device that energizes and communicates with passive NFC tags, smart cards, and peer devices over a 13.56 MHz magnetic field. NFC reader ICs sit inside the broader RFID / contactless / wireless-charging adjacent semiconductor taxonomy and typically convert the host's digital commands into amplitude-modulated RF and demodulate the load-modulated response from the card. They are critical building blocks for payment terminals, access control, ticketing, pairing, and IoT identification. Key features of the PR5331C3HN include 13.56 MHz operation across multiple air-interface standards (FeliCa, ISO 14443 A/B, MIFARE), dual digital host interfaces (USB and HSU), an integrated 32-bit microcontroller with on-chip ROM firmware, and a 40-VFQFN Exposed Pad footprint for compact surface-mount designs. The device handles peer-to-peer NFC communication and card emulation/reader modes through standard CCID and PC/SC driver stacks, making it attractive for OS-level integration on Windows, Linux and Android hosts. Technically, the PR5331C3HN uses a single-ended antenna driver with internal matching and an LDO-fed analog chain, achieving sub-milliwatt standby power while supporting full RF output into a 50 ohm-equivalent antenna tank during transmit. The integrated ROM implements the complete ISO/IEC 14443-3 Type A/B anticollision, MIFARE Classic crypto, and FeliCa polling sequences, so the host only sees abstracted APDU commands. The 40-pin QFN exposed pad ties to a quiet analog ground and provides a low thermal-resistance path for the ~30 mA peak RF current pulse. Typical applications include NFC readers for POS payment terminals, Windows-logon / physical-access badge readers, NFC pairing modules for Bluetooth/Wi-Fi devices, IoT identification nodes, and developer/evaluation boards. Its USB-only connection model makes it especially clean for PC-tethered designs where an internal MCU slot is precious. Over the air, the part achieves typical operating distances of 4-6 cm with a 50 mm loop antenna matched to the on-chip TX driver. When designing with the PR5331C3HN, lay the antenna within 30 mm of the chip to keep the matching network simple, and tie the exposed pad to a contiguous ground pour with multiple thermal vias to dissipate the RF-pulse current. Designers migrating from PN532 family parts should review the digital host interface selection carefully, because PR5331C3HN favors USB/HSU whereas PN532 typically uses SPI/I2C. This page synthesizes distributor pricing tiers, seven drop-in alternatives within the NXP CL/RC family, and practical design notes not consolidated in the manufacturer datasheet alone.
PR5331C3HN-C36051 - 13.56MHz USB NFC Reader IC | NXP
The NXP Semiconductors PR5331C3HN-C36051 is a highly integrated 13.56 MHz contactless NFC reader IC with USB 2.0 full-speed interface and dedicated firmware (C360,51 ROM code) for reader/writer operation, housed in a 40-pin HVQFN exposed-pad package. The part supports ISO/IEC 14443 Type A and B, FeliCa, MIFARE, and NFC Forum tag types, and includes an integrated microcontroller that offloads the host from real-time RF protocol handling. The /C360,51 suffix denotes a specific firmware variant configured for targeted reader applications. It supports 2.5V-3.6V supply on the PVDD rail and draws approximately 0.55 W during continuous RF operation. An NFC (Near Field Communication) reader IC is a contactless transceiver that powers a passive tag via an inductive RF field and demodulates the load-modulated response to exchange data. NFC readers sit at the bottom of the contactless stack: NFC -> contactless smartcard (ISO 14443) -> RFID 13.56 MHz -> short-range wireless -> RF & wireless IC. The PR533 family bridges a USB-equipped host (PC, embedded SBC, point-of-sale terminal) to contactless media such as payment cards, transit tickets, eID, and NFC Forum tags, eliminating the need for a separate protocol stack on the host CPU. Key features include a hardware cryptographic accelerator for MIFARE Classic Crypto1, integrated AFE for antenna matching, support for EMVCo contactless V2.0.1 in PCD mode (per the PR533 datasheet), and USB full-speed with USB 3.0 hub interoperability. Multiple host interfaces (USB, I2C, UART) provide flexibility for systems without an always-on USB host. The exposed thermal pad of the HVQFN package is critical for dissipating RF TX power during continuous polling. Architecturally, the PR5331C3HN combines an 80C51-compatible microcontroller core with a dedicated analog front end, an ISO 14443 / FeliCa RF interface, and a hardware USB 2.0 full-speed PHY. The C360 firmware variant implements the specific command set and tag-type support required by this MPN. Host communication happens over USB (primary), I2C/SPI/UART (secondary), keeping protocol latency off the application processor. Typical applications include USB NFC desktop readers, point-of-sale payment terminals, eID verification kiosks, transit ticketing readers, and industrial RFID read/write stations. The combination of USB bus-powered operation and integrated protocol stack makes it especially suited for plug-and-play reader accessories. When designing with this part, ensure the antenna matching network follows the NXP reference design (typically 50 ohm matched, with EMC filtering). The exposed pad must be soldered to a sufficiently large copper pour (>= 25 mm²) for thermal dissipation, and the USB DP/DM traces require 90 ohm differential routing per USB 2.0 specification. This page synthesizes distributor pricing, drop-in same-package alternatives, and application-specific design guidance not found in the manufacturer datasheet alone.
PR5331C3HN-C36055 - 13.56MHz NFC Reader IC, USB, 40-VFQFN | NXP
The NXP PR5331C3HN/C360:55 is a highly integrated transceiver IC with USB interface for contactless reader/writer communication at 13.56 MHz, housed in a 40-pin VFQFN exposed-pad package (HVQFN-40, 6x6 mm). It supports FeliCa, ISO 14443, and MIFARE contactless protocols and operates from 2.5 V to 3.6 V supply with 5 V USB compliance and 0.55 W dissipation. The device exposes both I2C and UART (HSU) host interfaces alongside USB for flexible system integration in NFC reader, payment, and access-control designs. The /C360:55 suffix designates a specific firmware/bond-out variant in the PR5331 family; an integrated microcontroller runs dedicated ROM code to handle multiple RF protocols offloading the host CPU. The 40-VFQFN package with exposed pad provides efficient thermal dissipation for the RF frontend while keeping PCB footprint compact for embedded reader modules. A contactless NFC/RFID reader IC is a radio-frequency transceiver that energizes and communicates with passive tags or cards using inductive coupling at 13.56 MHz (HF band). It belongs to the hierarchy: contactless reader -> NFC/RFID transceiver -> RF & wireless IC -> semiconductor. The PR5331 family targets ISO/IEC 14443 Type A/B, FeliCa, and NXP's MIFARE classic/Ultralight/DESFire tag families, plus peer-to-peer NFC. Designers typically add an external matching network, EMC filter, and antenna to form a complete reader front-end; the IC handles modulation, demodulation, framing, anti-collision, and crypto acceleration for MIFARE. Key features include support of FeliCa, ISO 14443, and MIFARE protocols on a single die, dual host links (USB plus I2C/UART HSU), low-power standby, integrated RF field detector, and a 40-VFQFN exposed-pad footprint for thermally robust designs. The exposed pad must be soldered to a continuous ground plane to meet EMC and thermal targets. The device is intended for designers who want a turnkey reader front-end rather than a discrete RF design. Technically, the PR5331C3HN integrates an RF analog front-end (transmitter, receiver, AGC), a digital protocol engine, and a microcontroller core running NXP firmware (ROM-resident for the /Cxxx variants). This partitioning removes host-side protocol stack overhead and lets the host treat the IC as a command/response peripheral over USB or HSU. Compared with software stacks using a generic 13.56 MHz front-end, the PR5331 shortens time-to-market for payment terminals, access readers, and NFC peer-to-peer use cases. Typical applications include USB NFC reader dongles, contactless payment terminals, physical access control readers, public transport / transit validators, and NFC peer-to-peer pairing kiosks. The integrated USB makes it especially attractive for PC-tethered reader peripherals and POS accessories. Designers should observe the matching-network reference design and EMC filter from the manufacturer datasheet, place the antenna within 5 cm of the IC, and provide a solid ground pour under the exposed pad. Note that /C360:55 is one firmware/bond-out option; other /Cxxx suffixes exist within the PR5331 family and may not be drop-in substitutes for firmware compatibility. This page consolidates distributor pricing, drop-in alternatives within the PR5331 family, and practical design notes that are not found in the manufacturer short data sheet.
PR5331C3HN-C370E - 13.56MHz USB NFC Reader IC | NXP | 40-HVQFN
The NXP Semiconductors PR5331C3HN-C370E is a highly integrated 13.56 MHz NFC/RFID transceiver with USB interface and embedded microcontroller firmware for contactless reader/writer applications, housed in a 40-pin HVQFN exposed-pad (SOT1449-1) package. Key specifications include 2.5V to 3.6V supply range, integrated ROM firmware supporting FeliCa, ISO 14443, ISO 14443A/B, ISO 18092 (NFCIP-1), MIFARE, and NFC Forum tag types, plus USB 2.0 full-speed and high-speed UART (HSU) host links. The C370E suffix denotes a specific firmware/feature variant locked into on-chip ROM. An NFC/RFID reader IC is a type of contactless transceiver that powers a nearby passive tag via an electromagnetic field at 13.56 MHz, modulates the field to exchange data, and decodes the tag response into a host-usable digital stream. In the broader hierarchy, NFC reader ICs sit under RFID transceivers -> RF ICs -> RF & Wireless semiconductors. NXP's CLRC663, PN5180, and PR5331 family dominate the 13.56 MHz infrastructure-reader segment where ISO 14443 / NFC Forum compliance, reader IC sensitivity, and host connectivity (USB / SPI / I2C / HSU) determine application fit. Key features of the PR5331C3HN-C370E include 13.56 MHz RF operation with a single external antenna, integrated firmware that eliminates external MCU protocol-stack development, USB 2.0 full-speed device interface for plug-and-play host connectivity, HSU (high-speed UART) link as a backup host interface, support for FeliCa / MIFARE Classic / MIFARE DESFire / ISO 14443 / NFC Forum tag types, and embedded contactless protocol handling by an integrated microcontroller. The 40-pin HVQFN EP package with exposed thermal pad enables compact USB-stick form factors and reader modules. The device architecture combines an RF front-end (transmitter, receiver, AGC, and framing logic), a digital protocol engine, an embedded 80C51-class microcontroller with dedicated ROM, and dual host interfaces (USB and HSU). The integrated firmware offloads command-set processing from the host CPU, so the host only exchanges reader-level APDUs over USB or HSU. Power is supplied from the USB VBUS rail at 5 V (regulated internally to 3.3 V) or from an external 2.5–3.6 V supply, with the IC drawing roughly 100–180 mA in active RF transmission depending on antenna matching. Typical applications include USB NFC readers for desktops and POS terminals, contactless smart-card readers for access control and ticketing, NFC peer-to-peer initiator devices, development kits for NFC tag testing, and embedded modules for vending machines, kiosks, and industrial handheld terminals. Its broad protocol coverage makes it well-suited for systems that must read mixed tag populations in retail, transport, and identity ecosystems. When designing with the PR5331C3HN-C370E, pay close attention to antenna matching network design - even a few nH of stray inductance at the TX1/TX2 pins will detune the matching circuit and reduce read range. Use NXP's NFC Cockpit configuration tool to load customer-specific firmware parameters, and ensure the HVQFN EP is soldered to a sufficiently large copper pour for thermal dissipation during continuous RF emission. This page consolidates verified distributor pricing, same-package drop-in alternatives, and engineering design notes that complement the manufacturer datasheet and shorten the bring-up time for new USB NFC reader designs.
QPA9510SR - 1W GaAs RF Power Amplifier 100-1000MHz | Qorvo
The Qorvo QPA9510SR is a high-power, high-gain, high-efficiency GaAs RF power amplifier IC covering 100 MHz to 1000 MHz, delivering up to 34 dB of maximum gain, +32 dBm of P1dB output power, and over 70 dB of analog gain-control range in a 16-QFN (3x3 mm) surface-mount package. An RF power amplifier is the final gain stage in a transmit chain, converting a modest driver signal into the high-power signal that feeds an antenna. Within the power-management and RF signal-chain hierarchy, it sits between the driver amplifier and the antenna switch or duplexer, and is a key determinant of transmit range, efficiency, and battery life in wireless systems. Key features of the QPA9510SR include a maximum gain of 34 dB, P1dB of +32 dBm suitable for roughly 1 W-class transmit applications, and an on-board analog power controller that provides more than 70 dB of gain adjustment. The controller also enables power-down: applying a logic-low control voltage places the device in standby mode, reducing current draw in duty-cycled transmitters. The device is manufactured on Qorvo's advanced GaAs (gallium arsenide) process technology, which provides high power-added efficiency and good thermal behavior at UHF frequencies. Bias flexibility allows designers to trade output power, linearity, and current consumption to match specific link-budget requirements, and the monolithic integration of the power controller reduces external component count compared with discrete PA plus controller solutions. Typical applications include the final RF amplifier stage in GSM hand-held equipment operating in the 900 MHz band, general-purpose UHF transmit chains between 100 MHz and 1000 MHz, and portable or battery-powered radios where standby power-down is required. The 3x3 mm QFN footprint suits compact hand-held and portable form factors. When designing with the QPA9510SR, verify bias settings against your linearity and efficiency targets, and manage thermal dissipation with adequate ground-pad copper since a +32 dBm GaAs PA dissipates substantial heat at full output. Consult the manufacturer datasheet for exact pin definitions and recommended matching networks before layout. This page synthesizes distributor availability, verified manufacturer data, application guidance, and practical design notes not found in the standard datasheet.
QPA9510TR7 - 880-915MHz GaAs GSM PA, 34dB Gain | Qorvo
The Qorvo QPA9510TR7 is a high-power, high-gain, high-efficiency GaAs RF power amplifier IC covering 880 MHz to 915 MHz (optimized within a 100 MHz to 1000 MHz general-purpose range) in a 16-QFN (3x3 mm) package. It delivers up to 34 dB of gain with a P1dB of +32 dBm and includes an on-board analog power controller. An RF power amplifier is the final gain stage in a transmitter chain, converting a driven RF signal into a high-power signal suitable for delivery to an antenna. Within the power management and signal chain hierarchy, the QPA9510 belongs to the power amplifier category of RF amplifiers, alongside low-noise amplifiers (LNAs), drivers, and general-purpose gain blocks. Key features include Qorvo's advanced GaAs process technology, a maximum small-signal gain of 34 dB, P1dB output power of +32 dBm (some distributor listings cite up to +35 dBm), and high efficiency for battery-operated handsets. An analog on-board power controller provides over 70 dB of gain adjustment range, allowing the output power to be precisely managed across the transmit burst. The integrated power controller also supports power-down: applying a logic-Low control voltage places the device in standby mode, minimizing current draw during idle slots. This makes the QPA9510 well suited to duty-cycled transmission protocols such as GSM/GPRS, where burst-mode operation dominates battery consumption. Typical applications include the final-stage RF amplifier in GSM hand-held equipment operating in the 900 MHz band, as well as UHF-band drivers and general-purpose power amplification from 100 MHz to 1000 MHz in cellular, FM, GPRS, and UHF wireless systems. When designing with the QPA9510, control the bias/gain-adjust pin with a clean, well-filtered analog voltage; controller bandwidth and control-line noise directly affect output power accuracy and spectral content. Verify thermal layout, since a +32 dBm P1dB device dissipates significant heat in a 3x3 mm QFN. This page synthesizes distributor listings, manufacturer product data, and practical design guidance not consolidated in the manufacturer datasheet.
QPK3000 - Fully Integrated UWB RTLS Module | Qorvo
The Qorvo QPK3000 is a fully integrated IR-UWB (impulse-radio ultra-wideband) RTLS tag module operating at 6.5 GHz to 8 GHz, with an integrated 2.4 GHz radio for Bluetooth Low Energy and/or IEEE 802.15.4-2020 connectivity, supplied from a 2.5 V to 3.6 V rail and housed in a 20 x 20 mm castellated-edge package with 1.5 mm pitch and two state-of-the-art integrated antennas. An RTLS (Real-Time Location System) tag module is a wireless device that transmits precisely timestamped UWB pulses, allowing infrastructure anchors to calculate position with centimeter-class accuracy - far beyond what Bluetooth RSSI or Wi-Fi positioning can achieve. Within the wireless hierarchy, UWB sits alongside BLE and IEEE 802.15.4 as a short-range PHY standard, but its wide bandwidth and narrow pulses give it unique ranging precision. The QPK3000 combines both radio domains on one certified module. Key features include dual-radio operation (UWB plus BLE/802.15.4 at 2.4 GHz), guaranteed interoperability with UWB-enabled enterprise infrastructure including leading Access Points, support for the Omlox standard and coming compatibility with Cisco Spaces, and a flexible Zephyr-based software environment for custom RTLS development. The integrated antennas eliminate RF layout work. Architecturally, the module is compliant with IEEE 802.15.4-2015 (PHY and MAC layers) and IEEE 802.15.4z-2020, enabling Enhanced Ranging Frame formats. Two UARTs are provided for interfacing with peripheral devices and for terminal logging during software development, which shortens bring-up time considerably. Typical applications include asset-tracking tags for smart factories, indoor navigation badges, and drop-in UWB RTLS addition to existing products without PCB redesign. The 2.5 V to 3.6 V supply range suits direct lithium-cell or regulated 3.3 V designs. Design consideration: because the module is certified and pre-integrated, the main engineering effort shifts to firmware (Zephyr RTOS) and mechanical placement of the two integrated antennas away from metal enclosures. This page synthesizes distributor data, ecosystem compatibility details, and practical integration guidance not found in a single manufacturer datasheet.
QPM1002 - 8.5-10.5GHz GaN X-Band T/R FEM 3W | Qorvo
The Qorvo QPM1002 is a Gallium Nitride (GaN) MMIC front-end module (FEM) for X-Band radar applications covering 8.5 GHz to 10.5 GHz, integrating a T/R switch, a low-noise amplifier, and a power amplifier in a 5 x 5 mm QFN surface-mount package with over-mold encapsulant. A front-end module (FEM) is a highly integrated RF building block that sits between the antenna and the transceiver in a radar system. In an X-Band phased array radar, the FEM performs three critical functions: amplifying weak received echoes (LNA path), amplifying transmitted pulses (PA path), and switching between the two (T/R switch). Integrating all three on a single GaN-on-SiC die reduces board area, assembly variation, and lattice-spacing constraints compared to discrete multi-chip solutions. According to the Qorvo datasheet, the receive path delivers 25 dB of small-signal gain with a low noise figure of 2.2 dB, maximizing radar detection range against small targets. The transmit path provides 33 dB of small-signal gain and can deliver 3 W of saturated output power with a power-added efficiency (PAE) of 32%. The ANT port tolerates up to 2 W of input power, eliminating the need for an external limiter diode and its associated insertion loss. The module is fabricated on Qorvo's QGaN25 0.25 um GaN-on-SiC process. The high thermal conductivity die-attach, combined with the over-molded QFN package, allows reliable operation in high-temperature environments typical of airborne and ground-based phased array antennas. Typical applications include X-Band phased array radar transmit/receive (T/R) channels, marine and weather radar, and airborne surveillance systems where compact size and high power density are mandatory. Design consideration: the high power density of GaN requires a well-designed thermal path; the exposed package paddle must be soldered to a low-thermal-resistance via array in the PCB. This page synthesizes distributor sourcing data, drop-in alternative guidance, and practical design notes not found in the manufacturer datasheet.
QPM1002SR - X-Band 3W GaN T/R FEM 8.5-10.5GHz | Qorvo
The Qorvo QPM1002SR is an 8.5-10.5 GHz GaN MMIC front-end module (FEM) integrating a T/R switch, low-noise amplifier, and power amplifier in a 5 x 5 mm over-molded QFN surface-mount package. The receive path provides 25 dB of gain with a 2.2 dB noise figure, while the transmit path delivers 33 dB small-signal gain, 3 W of saturated output power, and 32% power-added efficiency (PAE). A transmit/receive module is a bidirectional RF front end that shares a single antenna between a transmitter and a receiver using a T/R switch. In the system hierarchy, it sits above individual MMIC amplifiers, combining switching, LNA, and PA functions into one module, and is a core building block of power management for radar front ends. Modules like the QPM1002 reduce component count, footprint, and assembly tolerance compared to discrete chains. Key differentiating features include the integration of three functions (switch, LNA, PA) on a single die-level module, which minimizes interconnect losses and lattice pitch. According to Qorvo, the part is fabricated on the QGaN25 0.25 um GaN-on-SiC process, whose wide bandgap supports high power density and ruggedness. The over-mold encapsulant combined with a proprietary high-thermal-conductivity die-attach allows operation in elevated-temperature environments, and the compact 5 x 5 mm footprint supports the tight lattice spacing required by X-Band phased array radar. Technically, the GaN-on-SiC construction offers superior thermal conductivity relative to GaAs, enabling higher channel temperatures to be tolerated and higher power density per millimeter of gate periphery. The 0.25 um gate length of the QGaN25 process supports X-Band frequencies with good efficiency, and the integrated T/R switch eliminates the insertion loss of an off-module circulator or switch in compact arrays. Typical applications include X-Band phased array radar transmit/receive channels, military and commercial radar front ends, and airborne or ground-based surveillance radar systems. In phased arrays, the module's small size directly determines achievable element pitch at 8.5-10.5 GHz. When designing with this module, thermal management is the primary consideration: the GaN die dissipates substantial heat at 3 W RF output, so the PCB ground vias and heat-spreading copper must be designed for the high-thermal-conductivity die-attach to work as intended. Bias sequencing and switch control timing should follow the manufacturer datasheet. This page synthesizes distributor availability, verified datasheet parameters, and practical design guidance for the QPM1002SR not consolidated in the manufacturer datasheet.
QPM1002TR7 - 8.5-10.5GHz GaN T/R Module | Qorvo | X-Band Radar
The Qorvo QPM1002TR7 is an X-band GaN transmit/receive (T/R) front-end module covering the 8.5 GHz to 10.5 GHz frequency range, housed in a compact 24-pin QFN (5 x 5 mm) surface-mount package with over-mold encapsulant. It integrates the LNA and PA functions of an X-band radar front end in a single module. A transmit/receive module is the core building block of a radar front end: it switches and amplifies signals between the antenna and the transceiver, providing power amplification on transmit and low-noise amplification on receive. T/R modules sit at the top of the RF front-end hierarchy within RF integrated circuits, and in phased-array systems dozens to thousands of them are tiled behind antenna elements. Key features of the QPM1002 include its wide 8.5-10.5 GHz X-band coverage, gallium nitride (GaN) technology for high power density and efficiency, and a highly integrated single-module solution that replaces discrete PA, LNA, and switching functions. According to Qorvo, the 5 x 5 mm QFN over-molded package, coupled with a proprietary die-attach process, allows the QPM1002 to perform well in high-temperature environments. Technically, the module leverages Qorvo's GaN-on-SiC process, which provides superior thermal conductivity compared with GaAs, enabling higher output power in the same footprint and improved robustness against high junction temperatures. This makes the part well-suited to the duty-cycled, high-power operation typical of pulsed radar transmitters, where thermal management is often the limiting design factor. Typical applications include X-band phased-array radar for commercial and defense platforms, weather radar, marine radar, and radar altimetry. The compact size supports the tight lattice spacing required for X-band phased-array antenna tiles, where element spacing is on the order of half a wavelength at 10 GHz. When designing with the QPM1002, provide a low-inductance ground connection through the package center pad and follow the datasheet layout recommendations for bias decoupling at both RF ports; GaN devices also require correct power-up sequencing of gate and drain supplies to avoid damaging the transistors. This page synthesizes distributor availability data, manufacturer product information, and practical design guidance not found in any single source.
Quectel BC660K-GL-TE-B LTE Cat NB2 Module | Quectel
The Quectel BC660K-GL-TE-B is a high-performance multi-band LTE Cat NB2 (NB-IoT) module with extremely low power consumption, delivered in a compact LCC surface-mount package measuring 17.7 mm x 15.8 mm x 2.0 mm and weighing 1.8 g. It supports 3GPP LTE Cat NB2 with a maximum downlink rate of 127 Kbps and a maximum uplink rate of 158.5 Kbps across an extensive band set: B1/2/3/4/5/8/12/13/17/18/19/20/25/28/66/70/85, enabling near-global NB-IoT deployment on a single SKU. An NB-IoT (Narrowband Internet of Things) module is a low-power wide-area (LPWA) cellular transceiver defined by the 3GPP LTE Cat NB2 standard. Within the wireless communications hierarchy, it sits inside the LPWA family of cellular IoT technologies, alongside LTE Cat M1, and is optimized for applications that send small payloads infrequently while running for years on a single battery. Key features of the BC660K-GL-TE-B include the ultra-compact 17.7 mm x 15.8 mm x 2.0 mm LCC footprint for space-constrained designs, an extended operating temperature range of -40C to +85C for rugged environments, surface-mount technology (SMT) assembly suitable for high-volume automated production, and multi-band coverage for global carriers. The module's extremely low power consumption makes multi-year battery operation realistic for metering-grade devices. Technically, the BC660K-GL adopts LCC castellated-edge packaging, which provides reliable solder joints and resistance to vibration and shock, making it ideal for durable and rugged designs. Quectel documents a compatible-design migration path between the BC66/BC66-NA and BC660K-GL, allowing designers to move between NB-IoT generations on the same PCB concept with a documented compatible design manual. AT command control is shared with the BC950K-GL family via the common BC660K-GL/BC950K-GL AT Commands Manual. Typical applications include smart metering (water, gas, electricity), smart parking and bike sharing, smart city infrastructure, security and alarm systems, and asset tracking, where narrow bandwidth, deep coverage, and multi-year battery life outweigh raw throughput. Design consideration: because NB-IoT payloads are small and latency-tolerant, budget antenna selection and RF layout carefully per the Quectel BC660K-GL Reference Design and Hardware Design documents; RF matching network deviations from the reference design are the most common cause of failed carrier certification. This page synthesizes verified distributor data, the Quectel compatible-design migration path, and practical design guidance not consolidated on the manufacturer product page alone.
RAK2247 - SX1301 LoRa Concentrator mPCIe Module | RAKwireless
The RAKwireless RAK2247 is a mini-PCIe LoRa gateway concentrator module based on the Semtech SX1301 baseband processor, delivering up to 10 programmable parallel demodulation paths across 2 SX125x Tx/Rx front-end stages. Housed in a 50.95 mm × 30 mm PCI Express Mini Card form factor, the module supports US915 (and other regional ISM bands via SKU variants) and targets smart-metering fixed networks plus IoT deployments up to 500 nodes per km² in moderately interfered environments. A LoRa concentrator is a gateway-side baseband processor that turns a host embedded platform (any board exposing a free mPCIe slot) into a multi-channel LoRaWAN gateway. Within the broader wireless taxonomy the part sits at: LoRa concentrator -> LPWAN gateway module -> RF module -> IoT gateway hardware. By exploiting Semtech's chirp-spread-spectrum demodulation in parallel on 8 (or 10) channels, it allows simultaneous reception of many LoRa packets on different spreading factors and frequencies, which is the fundamental capability that distinguishes an 8-channel gateway from a single-channel peer device. Key features include: SPI or USB host interface (SKU dependent), integrated GPS receiver input for packet timestamping, +27 dBm maximum TX power through the on-board power amplifier, and a Listen-Before-Talk preamble scanner. Operating from a 3.3 V supply drawn through the mPCIe edge connector, the RAK2247 simplifies gateway prototyping because the host only needs to load the Semtech HAL / sx1301_hal library and forward IP packets to a LoRaWAN network server such as ChirpStack or TTN. Technically the SX1301 sits between two SX1257 (or SX1255) transceivers feeding an IF chain into the digital demodulation block; the chip contains 8 LoRa demodulation paths plus one FSK/GFSK path and one narrow-band channel. The host CPU offloads packet CRC, de-whitening and address filtering to the SX1301 firmware, dramatically reducing the gateway CPU load compared to a soft-modem approach. RAK2247 is a complete subsystem: the SX1301 plus front-ends, TCXO, LNA, PA, balun, GPS connector and IPEX antenna connectors are all integrated on the single mPCIe board. Typical applications include LoRaWAN indoor gateway prototypes, smart-metering aggregation gateways, industrial IoT bridges, and Helium light-hotspot builds. The 10-path parallel demodulation is the dominant selection criterion when a deployment expects concurrent traffic from many SF7–SF12 nodes. When designing with RAK2247, ensure the host carrier board routes USB D+/D- or SPI pins (CS, CLK, MOSI, MISO, IRQ, RESET) to a free mPCIe socket, supplies a clean 3.3 V at 500 mA, and provisions an IPEX antenna pigtail for the LoRa port and a separate IPEX for GPS. This page synthesizes distributor pricing, same-brand and cross-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
RAK3172-8-SM-NI - LoRaWAN 868MHz Stamp Module, STM32WLE5, SMD | RAKwireless
The RAKwireless RAK3172-8-SM-NI is a compact, surface-mount LoRaWAN transceiver module based on the STMicroelectronics STM32WLE5CCU6 SoC, operating in the 864 MHz / 865 MHz / 868 MHz ISM bands with 2 V to 3.6 V supply, and supplied without an I-PEX antenna connector. It integrates an Arm Cortex-M4 MCU at 48 MHz with 256-Kbyte Flash and 64-Kbyte SRAM alongside a Semtech SX126x-compatible LoRa transceiver, delivering up to 15 km line-of-sight range at 5.22 mA receive current and 87 mA transmit current in a 15.5 x 15 mm SMD footprint. A LoRa module is a self-contained radio block that bundles an MCU, RF transceiver, matching network and crystal into a single reflow-solderable unit. LoRaWAN, the wider-area networking protocol layered on LoRa modulation, occupies the sub-GHz ISM spectrum and is the dominant low-power wide-area network (LPWAN) standard for battery-operated IoT deployments - a category that includes LoRa modules, LPWAN SoCs, RF transceivers, and wireless connectivity ICs. The RAK3172 sits at the lower end of this taxonomy, giving designers a pre-certified path to LoRaWAN Class A/B/C without exposing the SX126x register set or the STM32WLE5 radio peripherals. Key features include support for LoRa, (G)FSK and BPSK modulations, multiple regional bands (EU868 / IN865 / RU864), AT-command and RUI3 (RAKwireless Unified Interface v3) firmware modes, and a hardware sleep current measured in microamperes for coin-cell and Li-SOCl2 battery use. The integrated RF matching network and 32.768 kHz RTC crystal simplify host-board design, while exposed UART, SPI, I2C, ADC and GPIO lines let the module double as the application's main controller. Architecturally, the STM32WLE5 silicon mates an LPWAN radio block to a Cortex-M4 with FPU, providing hardware AES-256 for LoRaWAN payload encryption, an integrated DC-DC converter for the radio PA, and a sub-GHz front end that removes the need for an external SAW filter in most band plans. This depth of integration explains why the RAK3172 can match the range of earlier discrete-MCU + discrete-transceiver designs in a fraction of the PCB area. Typical deployments include battery-powered IoT sensors, smart agriculture probes, asset tracking, smart metering, environmental monitors, and LoRaWAN-to-Cellular gateways' downlink/uplink test fixtures. The wide -40 C to +85 C operating range covers industrial outdoor enclosures. A design tip: route the antenna trace on the host board only when the host owns the RF keep-out, since this -NI variant ships without an I-PEX connector and relies on a trace antenna or U.FL pigtail. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
RAK3172-9-SM-I - 9xx MHz LoRaWAN Module with IPEX | RAKwireless
The RAKwireless RAK3172-9-SM-I is a compact, low-power LoRaWAN transceiver module based on the STMicroelectronics STM32WLE5CC SoC, integrating an Arm Cortex-M4 32-bit core with 256 KB Flash and 64 KB SRAM alongside an embedded LoRa radio. The -9-SM-I suffix denotes the 902-928 MHz sub-band (915 MHz nominal center) variant with a surface-mount form factor and an IPEX/U.FL antenna connector footprint. The module measures 15.5 mm x 15.5 mm and operates over a 2.0 V to 3.6 V supply range. A LoRaWAN module is a long-range, low-power wireless data transceiver that uses Semtech's LoRa modulation to deliver multi-kilometer connectivity in sub-GHz ISM bands while consuming only microamps in sleep mode. LoRaWAN (Long Range Wide Area Network) is an open LPWAN protocol standardized by the LoRa Alliance that sits above LoRa modulation and defines the MAC layer, device classes, and join procedures used for massive IoT deployments. Key specifications include +20 dBm maximum RF output power, link budget supporting up to 15 km line-of-sight range, 5.22 mA typical receive current, 87 mA peak transmit current, and 1.69 uA sleep current. The module exposes SPI, UART, and I2C peripherals through a stamp-hole land pattern, enabling drop-in integration into host PCBs without RF design effort. System architecture is built around the STM32WLE5 single-chip solution, which fuses the application MCU and sub-GHz radio on a common silicon die, reducing BOM cost and bill of materials while retaining full LoRaWAN 1.0.3 Class A/B/C stack compatibility. Developers can use the RAK3172 Arduino library, AT command firmware, or the Zephyr RTOS BSP for embedded development. Typical applications include battery-powered wireless sensor networks, smart agriculture soil/irrigation telemetry, asset tracking and cold-chain logistics, smart metering for water/gas utilities, and LPWAN building automation. The IPEX connector enables external high-gain antenna mounting for chassis-mounted or outdoor enclosures. When designing with this module, place the IPEX connector trace away from switching nodes and ensure the host PCB provides adequate ground flooding under the antenna feed. For external SMA antenna routing, choose the -NI (no IPEX) variant and route the RF pad directly to the SMA connector - the -I variant is intended for IPEX-attached flex antennas. This page consolidates verified distributor pricing, parametric alternatives, and practical LoRaWAN design notes not duplicated in the RAK3172 datasheet.
RAK3172-9-SM-NI - LoRaWAN 915MHz Module, STM32WLE5, 15.5x15mm | RAKwireless
The RAKwireless RAK3172-9-SM-NI is a compact, low-power LoRaWAN transceiver module built around the STMicroelectronics STM32WLE5CCU6 SoC and supporting 915MHz, 920MHz, and 923MHz regional bands. The module is supplied in a 15.5x15 mm SMD package, operates from 2 V to 3.6 V, and is shipped without an integrated I-PEX antenna connector so designers can route the RF output to an external antenna or SMA pigtail. Per the RAKwireless datasheet, the module supports LoRaWAN 1.0.3 Classes A/B/C and exposes UART, SPI, and I2C host interfaces. A LoRaWAN module is a pre-certified radio transceiver that combines a long-range sub-GHz physical layer (typically based on Semtech SX126x or integrated equivalents inside the host SoC) with LoRaWAN MAC protocol firmware. These modules sit one level above a raw RF transceiver in the connectivity hierarchy and below the application MCU; they remove the burden of RF matching, antenna design, and regional regulatory certification, allowing engineers to add multi-kilometer wireless links to battery-powered IoT nodes. The RAK3172 integrates the LoRa modem directly inside the STM32WLE5CC application MCU, eliminating the external transceiver IC and shrinking BOM cost and PCB footprint. Key feature highlights include an LoRaWAN 1.0.3 Class A/B/C stack, a stated link range of up to 15 km in line-of-sight conditions, three low-power operating modes (transmit, receive, and sleep), and access to GPIO, ADC, and timers of the underlying Cortex-M4 host. The host runs an integrated LoRaWAN stack via AT commands or STM32Cube firmware, allowing rapid prototyping without external MCU glue logic. UART serves as the primary host interface for AT-command control, while SPI and I2C are exposed for direct MCU integration. The wide 2 V to 3.6 V supply range is well suited to single-cell Li-SoCl2, Li-ion, and 2x AA battery chemistries common in field-deployed sensors. The module is rated for an industrial operating temperature range of -40 C to +85 C. Its small 15.5x15 mm SMD footprint, combined with the absence of an I-PEX connector, makes it suitable for designs where the antenna is integrated on the host PCB (chip antenna or PCB trace) or routed via a pigtail to a chassis-mount SMA. Designers can leverage the Zephyr OS board support, RAK's AT-command firmware, or STM32Cube-based SDKs. Typical applications include battery-powered LoRaWAN end nodes, agricultural soil/moisture sensors, smart-city metering, asset tracking, and wireless alarm panels. Designers should evaluate antenna gain and ground clearance around the RF pad when migrating from the I-PEX-equipped RAK3172-9-SM-I to this no-I-PEX variant. A key design consideration is antenna selection: because the I-PEX connector is omitted, RF performance depends entirely on the external antenna implementation. A poorly matched antenna can reduce range by 10 dB or more. This page synthesizes distributor pricing, drop-in module alternatives, and field design notes that go beyond the manufacturer datasheet alone.
RAK3172-T - LoRaWAN Module, 20dBm, TCXO | RAKwireless | IoT
The RAKwireless RAK3172-T is a low-power, long-range LoRaWAN transceiver module based on the STMicroelectronics STM32WLE5CC RF System-on-Chip, delivering up to 20 dBm output power from a 2 V to 3.6 V supply in a compact 15.5 x 15 mm castellated SMD stamp package. The -T variant integrates a 32 MHz temperature-compensated crystal oscillator (TCXO) for superior RF frequency accuracy over the industrial -40C to +85C operating range. A LoRaWAN module is a complete wireless subsystem that implements the LoRaWAN 1.0.3 MAC protocol on top of LoRa spread-spectrum physical-layer modulation, sitting within the LPWAN (low-power wide-area network) family of radio technologies used across the industrial IoT stack. Unlike a bare LoRa transceiver IC, the RAK3172-T embeds the MCU, radio, and RF matching network, so a host board only needs a UART/SPI link and an antenna. Key features include compliance with LoRaWAN Class A, B, and C, support for both LoRaWAN networks and pure LoRa point-to-point communication, up to 15 km line-of-sight range, and low active current of approximately 5.22 mA RX / 87 mA TX. Interfaces include UART, SPI, and I2C, enabling AT-command operation via RAKwireless RUI3 firmware or custom STM32WL development with STM32CubeIDE. The STM32WLE5CC SoC integrates an Arm Cortex-M4 core with the sub-GHz LoRa radio on a single die, reducing BOM count and board area versus discrete transceiver-plus-MCU designs. Compatibility with The Things Network (TTN), ChirpStack, and Actility server platforms simplifies end-device provisioning. The TCXO reference delivers tighter frequency tolerance than the standard RAK3172 crystal version, improving duty-cycle compliance and link reliability at band edges (863-870 MHz EU868 / 902-928 MHz US915, depending on variant). Typical applications include battery-powered IoT sensors, smart metering, asset trackers, and agricultural or smart-city nodes where multi-kilometer range and multi-year battery life are essential. Design consideration: place the module near the board edge with a keep-out area beneath the antenna feed, and always verify your regional frequency variant (-8 for 868 MHz, -9 for 915 MHz) before ordering. This page synthesizes distributor pricing, drop-in module variants, and practical design notes not found in the manufacturer datasheet.
RAK3172-T-8-SM-I - LoRaWAN 868MHz STM32WLE5 WisDuo Module
The RAKwireless RAK3172-T-8-SM-I is a low-power, long-range LoRaWAN transceiver module based on the STMicroelectronics STM32WLE5CC SoC, integrating an Arm Cortex-M4 MCU core and Semtech SX126x LoRa radio in a single die. The -T-8-SM-I variant is the tape-and-reel packaged, 868 MHz EU868 band, SMD castellation module with IPEX antenna connector, operating from a 2V to 3.6V supply and delivering up to +20 dBm transmit power. A LoRaWAN module is a pre-certified, surface-mount wireless subsystem that combines a microcontroller, a sub-GHz radio transceiver, an RF matching network, and an antenna interface into a single reflow-solderable PCB module. Within the broader wireless hierarchy, a LoRaWAN module sits above a bare transceiver IC and below a complete LoRaWAN end-device; the module approach lets product designers skip RF layout certification and reuse already-approved LoRaWAN 1.0.3 stacks. The RAK3172 belongs to the LPWAN family of modules using Chirp Spread Spectrum (CSS) modulation for long range, low data rate, and robust urban penetration. Key specifications of the RAK3172-T-8-SM-I include a +20 dBm maximum TX output power, approximately 5.22 mA average receive current, and up to 87 mA peak current at full +20 dBm transmit output. The module is housed in a 15.5 mm × 15 mm SMD castellation package with an operating temperature range of -40°C to +85°C and an RF range of approximately 15 km line-of-sight. Communication interfaces supporting serial SPI, UART, and I2C peripherals are exposed through the castellated edge pads. The STM32WLE5CC SoC at the heart of the module embeds a Cortex-M4 core running up to 48 MHz with 256 Kbytes of Flash and 64 Kbytes of SRAM, alongside the Semtech SX1262-compatible radio IP. This single-die integration removes the SPI bus between MCU and radio that earlier discrete designs required and reduces BOM cost. The module is pre-certified for the EU868 LoRaWAN band and supports Class A, B, and C end-device classes per LoRaWAN 1.0.3 specification. Typical applications for the RAK3172-T-8-SM-I include battery-powered IoT sensors for smart agriculture soil moisture monitoring, livestock asset tracking, smart metering for gas and water utilities, environmental monitoring stations, and industrial equipment predictive maintenance nodes. The IPEX antenna connector allows external antenna selection per deployment scenario, and the small 15.5 × 15 mm footprint fits inside compact enclosures. When designing with this module, ensure the host PCB exposes the IPEX connector footprint if an external antenna is planned, and add at least 10 µF of bulk decoupling near the module supply pin. The castellation pads are the only electrical connection - hand soldering requires a hot plate or precise iron tip. Confirm regional LoRaWAN band selection before purchasing: the -8- variant is for EU868, while other variants cover US915, AU915, AS923, IN865, and KR920 regions. This page synthesizes distributor pricing, drop-in same-band variants, and practical design considerations beyond the manufacturer datasheet, providing an engineering-grade resource for module selection and PCB integration.
RAK3172-T-9-SM-I - LoRaWAN 9 LoRa Module | RAK3172 WisDuo LPWAN
The RAK3172-T-9-SM-I is a compact, low-power LoRaWAN transceiver module based on the STMicroelectronics STM32WLE5CCU6 SoC, housed in a 15.5 x 15 mm surface-mount package with an integrated IPEX antenna connector. It supports LoRa and FSK modulation across the 9-band (902-928 MHz, US915/AU915/AS923 sub-bands) and operates from a 2 V to 3.6 V supply at 87 mA continuous transmit current and 5.22 mA receive current, with a stated link range of up to 15 km line-of-sight. A LoRa module (LoRaWAN transceiver) is a radio-frequency sub-system that implements the physical layer of the LoRaWAN low-power wide-area networking protocol defined by the LoRa Alliance. Within a wireless IoT node hierarchy, a LoRa module sits below the sensor/MCU logic, above the antenna matching network, and is governed by class-A/B/C MAC behavior for uplink/downlink scheduling on sub-GHz ISM frequencies in unlicensed bands. Key features of the RAK3172-T-9-SM-I include ultra-low-power sleep current suitable for battery-operated nodes, integrated ARM Cortex-M4 application core inside the STM32WLE5, native LoRaWAN 1.0.3 Class A/B/C firmware compatibility, and an SPI/UART/I2C host interface for external sensor integration. The IPEX MHF4 antenna connector simplifies field-replacement antenna selection and supports external high-gain antennas. The architecture combines STMicroelectronics' STM32WLE5 SoC with an on-board TCXO and RF matching network; this delivers improved frequency stability across temperature and reduced phase noise compared with XTAL-only designs. Internal DC-DC and LDO regulation allow the module to operate directly from 2 V to 3.6 V sources including single-cell Li-SoCl2 primary batteries. Typical applications include long-range battery-powered IoT sensors, agricultural and environmental telemetry nodes, smart-metering AMR/AMI endpoints, asset tracking, and industrial SCADA wireless extensions. Engineers choose the RAK3172 family for design-reuse compatibility across global LoRaWAN regional bands (8/EU868, 9/US915, AS923) via the trailing band code in the ordering scheme. When designing with this module, ensure the host PCB reserves a clearance keep-out beneath the IPEX connector, and verify host-MCU UART logic levels are 3.3 V tolerant. Sleep-mode firmware configuration (STM32WL STOP2/STANDBY) is required to meet the uA-class standby current claims needed for multi-year battery life. This page synthesizes distributor stock, regional band ordering variants, and practical design notes that the manufacturer datasheet alone does not compile in a single view.