10M08DCV81I7G vs 10M08DFV81C8G 比較
詳細な並列比較: 10M08DCV81I7G メーカー: Altera および 10M08DFV81C8G メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 10M08DCV81I7G | 10M08DFV81C8G |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $26.85 | $7.40 |
| Product Family | MAX 10 | — |
| Logic Elements (LE) | 8000 | — |
| Embedded User Flash | 387072 bit (378 Kbit) | — |
| Maximum User I/Os | 56 | — |
| Package Type | 81-ball WLCSP (UFBGA, wafer-level chip-scale package) | — |
| Process Node | [DATA_NEEDED: process node] | — |
| Configuration Memory | On-chip dual-configuration flash, instant-on | Internal (instant-on, no external flash required) |
| Embedded ADC | 12-bit SAR ADC (1 Msps) [DATA_NEEDED: number of channels] | — |
| 動作温度 | Industrial -40C to +100C (I7 grade) | 0C to +85C (Commercial) |
| Supply Voltage Core | [DATA_NEEDED: VCC core voltage] | — |
| I/O Bank Count | [DATA_NEEDED: number of I/O banks] | — |
| I/O Standards Supported | LVCMOS, LVTTL, LVDS, SSTL, RSDS | — |
| Memory Interfaces | DDR3, DDR3L, LPDDR2 (external PHY required) | — |
| PLL Count | [DATA_NEEDED: number of PLLs] | — |
| Global Clock Networks | [DATA_NEEDED: clock network count] | — |
| Configuration Modes | JTAG, Active Serial (AS), Passive Serial (PS) | — |
| 実装タイプ | Surface Mount (WLCSP - requires underfill) | Surface Mount (Wafer Level Chip Scale) |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| RoHS ステータス | Compliant | Compliant |
| Design Software | Intel Quartus Prime (MAX 10 device support) | — |
| Series | — | MAX 10 |
| Logic Elements | — | 8,000 |
| Embedded Memory (User Flash) | — | 387,072 bits |
| Total RAM Bits | — | 378 Kbits |
| Number of Logic Array Blocks (LABs) | — | 500 |
| Number of I/O | — | 56 |
| Embedded 18x18 Multipliers | — | 56 |
| Technology | — | 55 nm embedded flash CMOS |
| Core Voltage | — | 1.2 V |
| Speed Grade | — | 8 |
| パッケージ | — | 81-ball WLCSP (V81) |