5CSEBA2U19C6N vs 5CSEBA4U19C6N 比較
詳細な並列比較: 5CSEBA2U19C6N メーカー: Intel および 5CSEBA4U19C6N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 5CSEBA2U19C6N | 5CSEBA4U19C6N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $74.60 | $74.50 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 25 K | 40,000 (40K LE) |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Clock Frequency | 925 MHz | — |
| DSP Blocks | Variable-precision DSP | Variable-precision DSP blocks (18x18 multipliers) |
| パッケージ | 484-pin UBGA (19x19 mm) | 484-pin UFBGA / UBGA (19x19 mm) |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| Operating Temperature Grade | Commercial (other) | — |
| Memory Interfaces | DDR2, DDR3, LPDDR2 with ECC | — |
| HPS Peripherals | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC | — |
| L2 Cache | 512 KB shared | — |
| L1 Cache per Core | 32 KB I-cache + 32 KB D-cache | — |
| FPGA-to-HPS Bridges | AXI-32/AXI-64, FPGA-to-SDRAM ports | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| RoHS ステータス | Compliant | Compliant |
| Hard Processor System (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Maximum HPS Clock Frequency | — | 925 MHz |
| FPGA User I/O | — | 161 (per Altera product page) |
| Memory Controller | — | Hard controller for DDR2 / DDR3 / LPDDR2 |
| Embedded Memory | — | M10K memory blocks |
| Encryption Support | — | AES encryption (per LCSC listing) |
| Error Detection | — | SEU error detection and correction support |
| 動作温度 | — | 0C to +85C (commercial grade) |