5CSXFC6C6U23C8N vs 5CSXFC6C6U23I7LN 比較
詳細な並列比較: 5CSXFC6C6U23C8N メーカー: Intel および 5CSXFC6C6U23I7LN メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 5CSXFC6C6U23C8N | 5CSXFC6C6U23I7LN |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $445.00 | $119.55 |
| Family | Cyclone V SX (SoC FPGA) | Cyclone V SX SoC FPGA |
| Series | Cyclone V SX | — |
| Architecture | MCU + FPGA (Hard Processor System + FPGA fabric) | — |
| Logic Elements | 110,000 | 110K |
| Process Technology | 28 nm low-power (TSMC) | 28 nm low-power |
| Core Voltage | 1.1 V | — |
| Hard Processor System (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| Processor Maximum Frequency | 600 MHz | — |
| HPS L1 Cache | 32 KB instruction + 32 KB data per core | — |
| HPS L2 Cache | 512 KB shared | — |
| DSP Blocks | Variable-precision DSP (number not specified in retrieved data) | Variable-precision, supports 18x18 and 27x27 multipliers |
| Embedded Memory | M10K blocks (total Kbits [DATA_NEEDED: total embedded memory Kbits]) | [DATA_NEEDED: total Kbits] |
| Transceivers | Up to 3.125 Gbps integrated transceivers | Integrated high-speed transceivers |
| Maximum User I/O | 145 user I/O (per DigChip summary; full count per package [DATA_NEEDED: package pinout max user I/O]) | — |
| Memory Controller | Hard controller supporting DDR2, DDR3, LPDDR2 | — |
| パッケージ | 672-pin UFBGA (UBGA), 23x23 mm | 672-UBGA (23x23 mm) |
| 実装タイプ | Surface Mount (BGA) | Surface Mount (BGA) |
| 動作温度 | -40C to +100C (industrial grade, code C) | -40C to +100C (Industrial) |
| MSLレベル | 3 (per JEDEC J-STD-020, typical for large BGA) | — |
| RoHS ステータス | Compliant | Compliant |
| Lead-Free / Halogen-Free | Yes (lead-free BGA; halogen status [DATA_NEEDED: halogen-free yes/no]) | — |
| Speed Grade | C8 (commercial speed grade 8) | — |
| Lifecycle | Active (Cyclone V family in production) | — |
| Device Variant | — | 5CSXFC6C6U23 |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum HPS Clock Frequency | — | 925 MHz |
| HPS Peripherals | — | USB, GbE, SD/SDIO/MMC, UART, SPI, I2C |
| Memory Interfaces | — | DDR3, DDR2, LPDDR2 |
| I/O Standards | — | LVDS, LVCMOS, SSTL |
| Configuration | — | HPS boot from NAND/NOR/SD/eMMC; FPGA via Quartus Prime |