5M240ZT100I5N vs 5M240ZT100A5N 比較
詳細な並列比較: 5M240ZT100I5N メーカー: Altera および 5M240ZT100A5N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 5M240ZT100I5N | 5M240ZT100A5N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $4.81 | $6.10 |
| Family | MAX V | MAX V |
| Series | 5M240Z | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements | 240 | — |
| Macrocells | 192 | — |
| User Flash Memory | 8 Kbit | — |
| Maximum User I/O | 114 | — |
| User I/O Pins (per datasheet) | 79 | — |
| ピン数 | 100 | — |
| Package Type | TQFP-100 (T100) | — |
| Package Body Size | 14 x 14 mm | — |
| Lead Pitch | 0.50 mm | — |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Bank Voltage (VCCIO) | 1.2 V to 3.3 V (bank-dependent) | — |
| Speed Grade | -5 | — |
| Maximum Internal Frequency | 118.3 MHz | — |
| Pin-to-Pin Delay (tPD1) | 7.5 ns (per datasheet header) | — |
| 動作温度 | -40 C to +100 C (Industrial) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| Configuration Memory | Non-volatile flash (instant-on) | Non-volatile flash |
| 実装タイプ | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Yes (LEAD FREE per datasheet header) | — |
| MSLレベル | [DATA_NEEDED: MSL Level] | — |
| AEC-Q100 Automotive | Not qualified (Industrial grade) | — |
| Device Logic Elements | — | 240 LE |
| Number of Macrocells | — | 192 |
| Number of I/O Pins | — | 79 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Internal Operating Frequency | — | 118.3 MHz |
| Programmable Type | — | In System Programmable |
| I/O Voltage Standards | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| 電源電圧 | — | 1.8 V |
| Operating Temperature Grade | — | Automotive AEC-Q100 |
| パッケージ | — | 100-pin TQFP |
| RoHS ステータス | — | Compliant |
| Lead-Free Status | — | Vendor Undefined (per distributor catalog) |