5M80ZM64C5N vs 5M40ZM64C5N 比較
詳細な並列比較: 5M80ZM64C5N メーカー: Altera および 5M40ZM64C5N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 5M80ZM64C5N | 5M40ZM64C5N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1.61 | $1.45 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture Family | MAX V | — |
| Macrocell Count | 64 macrocells | — |
| Propagation Delay | 7.5 ns | — |
| Maximum Internal Frequency | 118.3 MHz | 118.3 MHz |
| User I/O Count | 30 I/Os | — |
| Programmable Logic Type | FLASH | — |
| Technology | CMOS | — |
| パッケージ | 64-MBGA | 64-ball MBGA, 5 mm × 5 mm |
| Package Pin Count | 64 pins | — |
| 電源電圧 | [DATA_NEEDED: supply voltage] | — |
| 動作温度範囲 | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial) |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| RoHS ステータス | unknown | Compliant |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| JTAG Support | [DATA_NEEDED: JTAG support] | — |
| Family | — | MAX V |
| Device Logic Elements | — | 40 |
| Macrocells | — | 32 |
| Pin-to-Pin Logic Delay (tPD) | — | 7.5 ns |
| Supply Voltage - Core (VCCINT) | — | 1.8 V |
| I/O Voltage Banks | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V tolerant |
| Programmable I/O Pins | — | 30 (approximate, per MAX V 5M40Z datasheet family) |
| User Flash Memory | — | 8 Kbits |
| Configuration Method | — | Non-volatile flash, instant-on, single-chip |
| Programming Interface | — | JTAG (IEEE 1149.1) ISP |
| Standby Current (ICCSTBY) | — | 55 µA typical |
| 実装タイプ | — | Surface Mount (BGA) |