ATSAMA5D27C-LD1G-CUR vs ATSAMA5D27C-CUR 比較
詳細な並列比較: ATSAMA5D27C-LD1G-CUR メーカー: Microchip Technology および ATSAMA5D27C-CUR メーカー: Microchip Technology。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Microchip Technology
ATSAMA5D27C-LD1G-CUR - 500MHz Cortex-A5 MPU, 1Gb LPDDR2 SiP | Microchip
ATSAMA5D27C-LD1G-CUR ✓ 生産中
仕様比較
| パラメータ | ATSAMA5D27C-LD1G-CUR | ATSAMA5D27C-CUR |
|---|---|---|
| ブランド | Microchip Technology | Microchip Technology |
| カテゴリ | Microcontrollers | Microcontrollers |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $14.95 | $12.90 |
| Core Architecture | ARM Cortex-A5 with NEON and FPU | ARM Cortex-A5 (32-bit) with NEON and FPU |
| Maximum CPU Clock | 500 MHz | 500 MHz |
| Number of Cores | 1 | — |
| データバス幅 | 32-bit | — |
| Integrated Memory | 1 Gbit LPDDR2 SDRAM | — |
| パッケージ | 361-ball TFBGA (16x16 mm), 0.8 mm ball pitch | 289-LFBGA (14 x 14 mm, 0.8 mm pitch) |
| 動作温度 | -40C to +85C (Industrial) | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount (Tape & Reel) |
| Series | SAMA5D2 | — |
| メモリタイプ | LPDDR2 (System-in-Package) | — |
| Memory Bus Width | 32-bit | — |
| LCD Controller | Yes (TFT, up to 2048x2048) | — |
| Ethernet | 10/100 MAC with IEEE 1588 (EMAC + GMAC) | 10/100 MAC with IEEE 1588 (EMAC) |
| USB | USB 2.0 High-Speed Host and Device | USB 2.0 HS Host + HS OTG + HS Device (3 ports) |
| Security | AES, SHA, TRNG, secure boot | — |
| Touch Controller | Peripheral Touch Controller (PTC) | Peripheral Touch Controller (PTC) |
| RoHS ステータス | Compliant | Compliant |
| Core Count | — | 1 |
| Cache (I-cache / D-cache) | — | 32 KB / 32 KB |
| Internal SRAM | — | 128 KB |
| ROM | — | 160 KB |
| External Memory Bus | — | 16-bit DDR2 / LPDDR / DDR3 / LPDDR3 |
| Operating Voltage (Core) | — | 1.2 V |
| 動作温度範囲 | — | -40 °C to +85 °C (industrial) |
| CAN | — | 2x CAN-FD controllers |
| Display Controller | — | TFT LCD up to 1024 x 768 |
| Audio Subsystem | — | Embedded (Class-D, I2S, SPDIF) |
| Cryptography | — | AES, SHA, TRNG, secure boot |
| Backup Mode Current | — | 5 µA typical (DDR in Self-Refresh) |