EP1810LC-30 vs EP1810LC-45 比較
詳細な並列比較: EP1810LC-30 メーカー: Altera および EP1810LC-45 メーカー: Rochester Electronics。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete仕様比較
| パラメータ | EP1810LC-30 | EP1810LC-45 |
|---|---|---|
| ブランド | Altera | Rochester Electronics |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $49.90 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 48 | — |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| 電源電圧 | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | — |
| パッケージ | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin PLCC (J-lead) |
| Programming | Device programmer or JTAG | — |
| 動作温度 | [DATA_NEEDED: temperature grade] | 0 °C to +70 °C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| ピン数 | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| RoHS ステータス | unknown (legacy ceramic package) | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| 実装タイプ | — | Surface Mount (PLCC socket compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |