EP1810LC-35T vs EP1810LC-25T 比較
詳細な並列比較: EP1810LC-35T メーカー: Intel および EP1810LC-25T メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810LC-35T | EP1810LC-25T |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $115.20 | $8.40 |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Usable Gates | 900 | Approx. 900 |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | CMOS, UV-erasable / OTP |
| Logic Compatibility | 100% TTL emulation | — |
| パッケージ | 68-pin PLCC (Plastic Leaded Chip Carrier) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Package Suffix | T = Tape and Reel | — |
| 動作温度 | 0 C to +70 C (Commercial) | 0 °C to +70 °C (commercial) |
| 実装タイプ | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | — |
| RoHS ステータス | Non-compliant (legacy PLCC product) | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Family | — | Altera Classic EP1810 |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Macrocells | — | 48 (4 quadrants x 12 macrocells) |
| Dedicated Inputs | — | 16 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Supply Voltage (VCC) | — | 5 V nominal |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |