EP1810LC-45 vs EP1810LI-35 比較
詳細な並列比較: EP1810LC-45 メーカー: Rochester Electronics および EP1810LI-35 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete仕様比較
| パラメータ | EP1810LC-45 | EP1810LI-35 |
|---|---|---|
| ブランド | Rochester Electronics | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $49.90 | $78.05 |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Logic Array Blocks | 4 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximum Operating Frequency | 22.2 MHz | — |
| Supply Voltage (Vcc) | 5 V (±5%) | — |
| Process Technology | 5 V CMOS EPROM | — |
| パッケージ | 68-pin PLCC (J-lead) | 68-pin PLCC (J-Lead, plastic) |
| 動作温度 | 0 °C to +70 °C (commercial) | -40 C to +85 C (industrial, 'I' suffix) |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| RoHS ステータス | [DATA_NEEDED: RoHS status of Rochester-sourced part] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | [DATA_NEEDED: lead-free status] |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Macrocells | — | 48 |
| Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Technology | — | CMOS, UV-erasable EPROM configuration cell |
| 電源電圧 | — | 5 V (TTL-compatible I/O) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| MSLレベル | — | [DATA_NEEDED: MSL rating] |