EP1810LI-35 vs EP1830-20CFN 比較
詳細な並列比較: EP1810LI-35 メーカー: Altera および EP1830-20CFN メーカー: Texas Instruments。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810LI-35 | EP1830-20CFN |
|---|---|---|
| ブランド | Altera | Texas Instruments |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $78.05 | $9.85 |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 35 ns | 22 ns |
| Speed Grade | 35 (slowest in EP1810L family) | -20 |
| パッケージ | 68-pin PLCC (J-Lead, plastic) | PLCC-68 (QCCJ, J-lead) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | CMOS EPROM |
| 電源電圧 | 5 V (TTL-compatible I/O) | — |
| 動作温度 | -40 C to +85 C (industrial, 'I' suffix) | — |
| 実装タイプ | Surface Mount (PLCC socket compatible) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSLレベル | [DATA_NEEDED: MSL rating] | — |
| Macrocell Count | — | 48 |
| Maximum Supply Voltage | — | 5.25 V |
| I/O Pins | — | 48 |
| Dedicated Inputs | — | 12 |
| Terminal Pitch | — | 1.27 mm |
| Terminal Form | — | J-Bend |
| Package Code | — | QCCJ |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Commercial (0C to 70C) |
| Typical Operating Current | — | 20 mA at 1 MHz |
| Maximum Counter Frequency | — | 50 MHz (4 x 12-bit counters) |
| Configuration Memory | — | Non-volatile EPROM (UV-erasable) |