EP1K30TC144-3 vs EP1K10TC144-3 比較
詳細な並列比較: EP1K30TC144-3 メーカー: Intel および EP1K10TC144-3 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1K30TC144-3 | EP1K10TC144-3 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.80 | $11.55 |
| Series | ACEX-1K | — |
| Logic Elements / Cells | 1,728 | 576 |
| Total RAM Bits | 24,576 | — |
| Number of LABs/CLBs | 216 | — |
| Typical Gates | 30,000 | 10,000 |
| Maximum System Gates | 56,000 | — |
| Number of User I/O | 102 | — |
| Number of Logic Array Blocks | 216 | — |
| Supply Voltage (Core) | 2.5 V | — |
| I/O Voltage Standard | 2.5 V LVCMOS / LVTTL (MultiVolt up to 5.0 V tolerant) | — |
| Process Technology | 0.22 µm SRAM | 0.22 µm CMOS |
| Operating Temperature (Commercial) | 0C to +70C | — |
| パッケージ | 144-LQFP / 144-TQFP (22x22 mm, 0.5 mm pitch) | 144-LQFP (TQFP) |
| 実装タイプ | Surface Mount | Surface Mount |
| Speed Grade | -3 (slowest speed bin) | -3 |
| Configuration Method | Serial configuration device (EPC2/EPC8 compatible) | SRAM, JTAG IEEE 1149.1 |
| Boundary Scan | IEEE 1149.1 JTAG compliant | — |
| Number of Global Clocks | 8 | — |
| RoHS ステータス | [DATA_NEEDED: rohs status from datasheet] | — |
| Family | — | ACEX-1K |
| Embedded RAM Bits | — | 12,288 |
| Embedded Array Blocks (EABs) | — | 4 |
| User I/O Pins | — | 92 |
| Maximum Internal Frequency | — | 200 MHz |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 3.3 V |
| 動作温度 | — | 0C to +70C (commercial) |