EP1K30TI144-3 vs EP1K30TC144-3 比較
詳細な並列比較: EP1K30TI144-3 メーカー: Altera および EP1K30TC144-3 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1K30TI144-3 | EP1K30TC144-3 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.40 | $10.80 |
| Product Type | FPGA (Field Programmable Gate Array) | — |
| Series | ACEX 1K | ACEX-1K |
| Typical Gate Count | 30,000 gates | — |
| Logic Elements | 1,728 | — |
| Embedded Memory (RAM bits) | 24,576 bits | — |
| Maximum User I/O | 102 | — |
| Dedicated Input Pins | 6 | — |
| Total Package Terminals | 144 | — |
| Supply Voltage VCCINT | 2.5 V (min 2.375 V, max 2.625 V) | — |
| I/O Logic Levels | 1.8 V / 2.5 V / 3.3 V (multi-voltage I/O banks) | — |
| 動作温度 | -40 °C to +85 °C (industrial) | — |
| パッケージ | 144-pin TQFP (LQFP, 0.5 mm pitch) | 144-LQFP / 144-TQFP (22x22 mm, 0.5 mm pitch) |
| Speed Grade | -3 | -3 (slowest speed bin) |
| Temperature Grade Code | TI (Industrial) | — |
| Configuration Method | SRAM-based, JTAG (IEEE 1149.1) / serial/parallel PROM | Serial configuration device (EPC2/EPC8 compatible) |
| Process Technology | CMOS | 0.22 µm SRAM |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status not in provided data] | [DATA_NEEDED: rohs status from datasheet] |
| Logic Elements / Cells | — | 1,728 |
| Total RAM Bits | — | 24,576 |
| Number of LABs/CLBs | — | 216 |
| Typical Gates | — | 30,000 |
| Maximum System Gates | — | 56,000 |
| Number of User I/O | — | 102 |
| Number of Logic Array Blocks | — | 216 |
| Supply Voltage (Core) | — | 2.5 V |
| I/O Voltage Standard | — | 2.5 V LVCMOS / LVTTL (MultiVolt up to 5.0 V tolerant) |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Boundary Scan | — | IEEE 1149.1 JTAG compliant |
| Number of Global Clocks | — | 8 |