EP1K50FC256-2 vs EP1K50XXB 比較
詳細な並列比較: EP1K50FC256-2 メーカー: Altera および EP1K50XXB メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1K50FC256-2 | EP1K50XXB |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $62.00 | $10.90 |
| Series | ACEX-1K | — |
| Family | ACEX 1K Family | ACEX-1K |
| Logic Cells / Elements | 2,880 | — |
| Typical Gates | 50,000 | 50,000 |
| Number of LABs/CLBs | 360 | — |
| User I/Os | 186 | — |
| Total RAM Bits | 40,960 | — |
| Number of Gates | 50,000 | — |
| Voltage - Supply | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Process Technology | 0.22 µm CMOS | 0.18 um SRAM |
| Propagation Delay | 0.4 ns (per Partstack listing) | — |
| 動作温度 | 0°C to +70°C (commercial) | Commercial 0C to +70C / Industrial -40C to +85C |
| パッケージ / ケース | 256-BGA (FineLine BGA, 17x17 mm) | — |
| 実装タイプ | Surface Mount | — |
| 実装スタイル | SMD/SMT | — |
| Programming Type | In-System Programmable via JTAG (IEEE 1149.1) | — |
| Configuration Method | SRAM-based, volatile configuration | Serial configuration device or JTAG |
| RoHS ステータス | Compliant | Compliant (lead-free variants available) |
| REACH Status | Compliant | — |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements (LEs) | — | 2,880 |
| Embedded System RAM Bits | — | 40,960 |
| Embedded Array Blocks (EABs) | — | 10 (each 4 Kbit, configurable as RAM/ROM) |
| Maximum User I/O | — | [DATA_NEEDED: depends on package variant] |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 3.3 V / 2.5 V / 1.8 V (multi-voltage) |
| In-System Programmability | — | Yes, via JTAG (IEEE 1149.1) |
| Package Type | — | [DATA_NEEDED: depends on MPN suffix] |
| ライフサイクル状態 | — | Obsolete (NRND on legacy Altera roadmap) |