EP1K50FI256-2N vs EP1K50F256-2N 比較
詳細な並列比較: EP1K50FI256-2N メーカー: Altera および EP1K50F256-2N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1K50FI256-2N | EP1K50F256-2N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $23.90 | $21.80 |
| Series | ACEX-1K | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 2,880 | 2,880 |
| Number of LABs/CLBs | 360 | — |
| Total RAM Bits | 40,960 | 40,960 |
| Number of Gates | 50,000 (typical); 199,000 (maximum) | — |
| Number of I/O Pins | 186 (maximum) | — |
| Core Voltage | 2.5 V (2.375 V to 2.625 V) | 3.3 V |
| Operating Frequency (max) | 200 MHz (internal) | — |
| Process Technology | 0.22 µm CMOS, SRAM-based | 0.22 µm SRAM |
| パッケージ | 256-ball FineLine BGA (FBGA), 17 x 17 mm, 1.8 mm height | 256-ball FineLine BGA (F256), 1.0 mm pitch |
| 実装タイプ | Surface Mount | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Configuration Method | SRAM - serial/parallel, JTAG (IEEE 1149.1), EPC configuration PROM | SRAM, serial or parallel via Altera EPC devices |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free / halogen-free status] | — |
| Family | — | ACEX 1K |
| Typical Gates | — | 50,000 |
| Logic Array Blocks (LABs) | — | 360 |
| Embedded Array Blocks (EABs) | — | 5 |
| Maximum User I/O | — | 186 |
| Speed Grade | — | -2 |
| I/O Standards | — | LVTTL, LVCMOS, 3.3 V / 2.5 V / 1.8 V / 1.5 V |
| Programming Interface | — | JTAG (IEEE 1149.1) / in-system programmable |