EP1M120F484I6M vs EP1M120F484C8ES 比較
詳細な並列比較: EP1M120F484I6M メーカー: Altera および EP1M120F484C8ES メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1M120F484I6M | EP1M120F484C8ES |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $325.00 | $119.40 |
| Family | Mercury (EP1M) | ACEX 1M |
| Logic Elements | 120,000 | — |
| System Gates | 480,000 (typical) | — |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | — |
| Package Code | BGA, 484 balls, Fine-pitch | — |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Temperature Grade | Industrial | — |
| Speed Grade | -6 (slowest Mercury timing bin) | C8 (-8 speed bin) |
| 電源電圧 | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | LVTTL, LVCMOS, True-LVDS, PCI |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| RoHS ステータス | Compliant (M revision) | [DATA_NEEDED] |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements / Gates | — | 120,000 (120K gates) |
| Embedded Logic Cells (EABs) | — | 4,800 |
| User I/O Pins | — | 303 |
| パッケージ | — | 484-ball FineLine BGA |
| Sample Grade | — | ES (Engineering Sample) |
| Process Technology | — | 0.18 µm CMOS, SRAM-based |
| Embedded RAM | — | ~104 Kbits across 12 RAM blocks |
| PLLs | — | 4 enhanced PLLs |
| Operating Voltage (Core) | — | [DATA_NEEDED: core VCC range] |
| MultiVolt I/O Support | — | 1.5 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Configuration Method | — | SRAM bitstream, JTAG/serial |
| 動作温度 | — | [DATA_NEEDED: industrial/commercial grade temp range] |
| 実装タイプ | — | Surface Mount (BGA) |