EP1S25F1020C6N vs EP1S25F1020C6 比較
詳細な並列比較: EP1S25F1020C6N メーカー: Altera および EP1S25F1020C6 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1S25F1020C6N | EP1S25F1020C6 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $450.00 | $425.00 |
| Family | Stratix | Stratix |
| Logic Elements (LE) | 25,660 | — |
| Logic Cells | 25,660 | — |
| Embedded Memory (bits) | 1,944,576 | — |
| User I/O Pins | 706 | — |
| LABs (Logic Array Blocks) | 2,566 | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| パッケージ | 1020-ball FC-FBGA (33 x 33 mm, 1.0 mm pitch) | 1020-ball FC-FBGA (33 x 33 mm, 1 mm pitch) |
| Maximum Internal Clock Frequency | 450.05 MHz | — |
| 動作温度 | 0C to +85C (Commercial) | 0 C to +85 C (commercial extended) |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Configuration Method | JTAG or EPC configuration device | — |
| Family Generation | Stratix (1st generation) | — |
| Logic Elements | — | 25,660 |
| Logic Array Blocks (LABs) | — | 2,566 |
| Total Embedded Memory (bits) | — | 1,944,576 |
| User I/Os | — | 706 |
| Embedded Memory Type | — | TriMatrix (M512 + M4K + M-RAM) |
| DSP Blocks | — | Yes (hardware multipliers) |
| PLLs (Clock Management) | — | 6 |
| Core Supply Voltage | — | 1.5 V |
| Compliance / Lead-Free | — | Lead-free (per Altera family datasheet) |