EP1S80F1020C6 vs EP1S80F1020C5 比較
詳細な並列比較: EP1S80F1020C6 メーカー: Intel および EP1S80F1020C5 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1S80F1020C6 | EP1S80F1020C5 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1,180.00 | $745.00 |
| Series | Stratix | — |
| Logic Elements | 79,040 | 80,640 |
| Total RAM Bits | 7,427,520 | 7,427,520 |
| Number of Logic Blocks / LABs | 9,191 | — |
| Number of I/O Pins (max) | 773 user I/O | — |
| Number of Pins / Balls | 1020 | — |
| Package Type | FC-FBGA (flip-chip fine-pitch BGA), 33 x 33 mm, 1.0 mm pitch | — |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V nominal (1.425 V to 1.575 V) | — |
| Speed Grade | C6 | C5 |
| Operating Temperature (Commercial) | 0 C to +85 C | — |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| Maximum Internal Clock Frequency | 450.05 MHz | — |
| Family Description | FPGA - Field Programmable Gate Array | — |
| Embedded Memory | TriMatrix (three block sizes, true/simple dual-port) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial/parallel configuration device | — |
| Design Tool | Quartus II (legacy, Stratix family) | — |
| RoHS ステータス | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| 湿気感度レベル（MSL） | [DATA_NEEDED: MSL rating] | — |
| Family | — | Stratix |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| Logic Array Blocks (LABs) | — | 7,904 |
| Embedded DSP Blocks | — | 12 (9-bit × 9-bit multipliers) |
| PLLs | — | 12 |
| Maximum User I/Os | — | 773 |
| I/O Banks | — | 21 |
| パッケージ | — | 1020-ball FCBGA, 33 × 33 mm, 1 mm pitch |
| 動作温度 | — | 0 °C to 85 °C (Commercial) |
| 電源電圧 | — | Stratix core/I/O multi-rail (per datasheet) |
| Logic Family | — | CMOS |