EP1SGX25FF1020C7 vs EP1SGX25FF1020I7 比較

詳細な並列比較: EP1SGX25FF1020C7 メーカー: Altera および EP1SGX25FF1020I7 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP1SGX25FF1020C7 EP1SGX25FF1020I7
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $1,280.00 $210.00
Family Stratix GX Stratix GX
Logic Elements 25,660 —
Number of LABs/CLBs 2,566 —
Total RAM Bits 1,944,576 —
User I/O Count 607 —
Number of Gates [DATA_NEEDED: gate count not provided in source data] —
Supply Voltage - Core 1.425 V to 1.575 V —
実装タイプ Surface Mount Surface Mount (FC-FBGA)
パッケージ / ケース 1020-BBGA, FCBGA (33 x 33 mm, 1 mm pitch) —
Supplier Device Package 1020-FBGA (33x33) —
Logic Family CMOS —
動作温度 0 C to 85 C —
Lead Free Yes (per digchip datasheet) —
RoHS ステータス [DATA_NEEDED: not stated in source data] [DATA_NEEDED: RoHS compliance]
Max Operating Frequency (cited) 4385.97 MHz (per Arrow listing) —
Process Technology 1.5 V CMOS 130 nm CMOS
Series — EP1SGX25
Logic Cells — 25,660
Configurable Logic Blocks (CLBs) — 2,566
Core Supply Voltage — 1.5 V
パッケージ — FC-FBGA-1020 (Flip-Chip Fine-pitch BGA)
Number of Terminals / Balls — 1020
Terminal Form — Ball
Temperature Grade (suffix 'I') — Industrial
Speed Grade — 7 (highest production grade)
Terminal Pitch — [DATA_NEEDED: terminal pitch]
Combinatorial Delay per CLB — 9.48 ns (per Microchip USA listing)
Combinatorial Delay Variant — [DATA_NEEDED: tPD per CLB variant speed grade]
Maximum Internal Clock Frequency — [DATA_NEEDED: max Fmax in MHz per speed grade]
Embedded Transceivers — Yes (Stratix GX feature)
Configuration Method — SRAM-based (volatile, requires configuration at power-up)
MSLレベル — [DATA_NEEDED: MSL level]

データシート&リソース

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