EP20K1000CF33C9ES vs EP20K1000CF672C7GZ 比較
詳細な並列比較: EP20K1000CF33C9ES メーカー: Altera および EP20K1000CF672C7GZ メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K1000CF33C9ES | EP20K1000CF672C7GZ |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $215.00 | $162.40 |
| Family | APEX-20KC | APEX 20KC |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| Typical Gate Count | 1,000,000 system gates | — |
| Logic Elements | 38,400 | — |
| Logic Array Blocks (LABs) | 3,840 | — |
| Embedded System Blocks (ESBs) | 212 | — |
| Total Embedded RAM Bits | 327,680 bits | — |
| Maximum User I/O Pins | 708 | — |
| パッケージ | 1,020-ball FineLine BGA (FBGA) | — |
| Speed Grade | C9 | C7 (7 ns pin-to-pin delay, commercial) |
| 動作温度 | 0 C to +85 C (commercial) | 0°C to +85°C |
| Process Technology | 0.18 um CMOS | 0.15 µm CMOS |
| Logic Element Architecture | 4-input LUT with dedicated carry chain | — |
| Maximum Embedded RAM per ESB | 32,768 bits (dual-port, FIFO support) | — |
| Phase-Locked Loops | Up to 4 enhanced PLLs | — |
| MultiVolt I/O Support | 1.8V / 2.5V / 3.3V / 5.0V | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Configuration Method | Passive serial / Passive parallel / JTAG | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free finish status] | — |
| Series | — | APEX-20KC® |
| System Gates | — | 1,000,000 |
| Logic Elements / Cells | — | 38,400 |
| Total RAM Bits | — | 327,680 |
| Number of I/O | — | 508 |
| Number of LABs/CLBs | — | 2560 |
| Number of EABs | — | 160 |
| Number of Logic Elements per EAB | — | 2048 bits |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| パッケージ / ケース | — | 672-FBGA (672-BBGA) |
| Supplier Device Package | — | 672-FBGA (27x27 mm, 1.27 mm pitch) |
| 実装タイプ | — | Surface Mount |
| Lead Free | — | Yes |