EP20K100EBC652-2X vs EP20K300EBC652-2 比較
詳細な並列比較: EP20K100EBC652-2X メーカー: Altera および EP20K300EBC652-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K100EBC652-2X | EP20K300EBC652-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Unknown |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $85.00 | $384.08 |
| Family | APEX 20KE | — |
| Typical Gates | 100,000 | — |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | — |
| Embedded System Blocks (ESBs) | 26 | — |
| Maximum RAM Bits | 53,248 | — |
| Maximum User I/O Pins | 246 | — |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | — |
| パッケージ | 652-ball BGA (EBC652) | 652-BGA |
| Speed Grade | -2 (faster commercial) | — |
| Process Technology | 0.18 µm CMOS, SRAM-based | — |
| 動作温度 | 0C to +85C (commercial) | [DATA_NEEDED: operating temperature range] |
| 実装タイプ | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | — |
| Clock Resources | Up to 4 DLLs, multiple global clocks | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | unknown |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Device Family | — | APEX-20KE |
| Logic Cells | — | 11520 |
| Macros | — | 1152 |
| Total RAM Bits | — | 147456 bits |
| I/O Count | — | 408 |
| 電源電圧 | — | 1.71 V to 1.89 V |
| Package Dimensions | — | 45 mm x 45 mm |
| Technology | — | 0.22 um (reported for family variant) |
| 最大クロック周波数 | — | 350 MHz (reported for family variant) |
| Configuration Technology | — | SRAM-based programmable logic (family description) |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |