EP20K200EBC356-1 vs EP20K200EBC356-2 比較
詳細な並列比較: EP20K200EBC356-1 メーカー: Altera および EP20K200EBC356-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K200EBC356-1 | EP20K200EBC356-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $142.00 | $99.50 |
| Family | APEX 20K (APEX 20KE) | APEX 20K (APEX 20KE enhancement) |
| System Gates | 200,000 | — |
| Logic Elements / Cells | 8,320 | — |
| Maximum User I/Os | 277 | — |
| Core Voltage | 1.8 V (1.71 V to 1.89 V) | — |
| Process Technology | 0.22 µm CMOS | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Internal Performance | Up to 367 MHz | — |
| パッケージ | 356-ball LBGA (35 x 35 mm) | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount (BGA) |
| 動作温度 | 0 °C to 85 °C (Commercial) | 0 C to 85 C (commercial) |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| On-chip Memory | Embedded System Blocks (ESB / SRAM) | — |
| Configuration Method | JTAG (ByteBlaster / MasterBlaster), passive serial | — |
| Development Software | Altera Quartus II | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status not stated in verified sources] | — |
| ライフサイクル状態 | Obsolete / EOL | — |
| Series | — | APEX 20KE |
| Typical Gates | — | 200,000 |
| Maximum Logic Elements | — | 8320 |
| Macros / Logic Cells | — | 832 |
| Maximum Flip-Flops | — | 13,824 |
| Embedded RAM | — | 53,248 bits |
| User I/Os | — | 271 |
| Number of Terminals / Pins | — | 356 (LBGA) |
| 電源電圧 | — | 2.5 V (core) |
| Logic Family | — | CMOS |
| Number of PLLs | — | 4 embedded PLLs |
| Number of DDR Interfaces | — | 4 |
| Package Type | — | 356-LBGA (EBC suffix) |
| Speed Grade | — | -2 |
| Compliance | — | RoHS status [DATA_NEEDED: RoHS] |