EP20K30EFC144-2X vs EP20K30EFC144-3 比較
詳細な並列比較: EP20K30EFC144-2X メーカー: Altera および EP20K30EFC144-3 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K30EFC144-2X | EP20K30EFC144-3 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $58.50 | $10.40 |
| Device Family | Altera APEX 20K | — |
| Device Type | Loadable programmable logic device (FPGA/CPLD hybrid) | — |
| Typical Gates | 30,000 gates | — |
| Number of Logic Elements / Cells | 1,200 cells (third-party parametric listing) | — |
| Number of Macrocells | 192 | — |
| Number of User I/O | 93 | — |
| Number of Terminals | 144 | — |
| Terminal Form | Ball | — |
| Package Code | LBGA / 144-FBGA | — |
| Package Shape | Square | — |
| Core Supply Voltage | 1.8 V | 1.71 V to 1.89 V |
| Process Technology | 0.22 um | 0.22 um |
| Speed Grade | -2X | -3 |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | [DATA_NEEDED: exact operating temperature range] | — |
| Embedded RAM Bits | [DATA_NEEDED: embedded memory size] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration Schemes | [DATA_NEEDED: supported configuration schemes] | — |
| RoHS ステータス | unknown | [DATA_NEEDED: RoHS status] |
| Series | — | APEX-20K |
| Family | — | APEX-20K FPGA |
| Logic Elements / Cells | — | 1200 |
| Total System Gates | — | 30,000 (typical) |
| Total RAM Bits | — | 24576 |
| Number of User I/Os (per pkg) | — | 92 (144-LQFP) |
| User I/Os (max per family) | — | 408 |
| Internal Operating Frequency | — | 160 MHz |
| Propagation Delay | — | 1.68 ns (typical) |
| Logic Family | — | CMOS |
| Architecture | — | MultiCore (LUT + product-term + ESB) |
| パッケージ / ケース | — | 144-LQFP (20x20 mm) |
| 動作温度 | — | 0C to +85C |
| Development Tool (legacy) | — | Quartus II / MAX+PLUS II |