EP20K400BC652-1X vs EP20K400GC655-1 比較
詳細な並列比較: EP20K400BC652-1X メーカー: Intel および EP20K400GC655-1 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete仕様比較
| パラメータ | EP20K400BC652-1X | EP20K400GC655-1 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $140.00 | $135.00 |
| Series | APEX 20KE | EP20K400 |
| Family | APEX 20K | APEX 20K |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | — |
| Embedded Memory (bits) | 212,992 | — |
| Embedded Array Blocks (EABs) | 104 x 2,048 bits | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 4 | 6 |
| PLLs | 4 | — |
| DLLs | 4 | — |
| Maximum Frequency | 250 MHz | — |
| Propagation Delay (pin-to-pin) | 2.5 ns | — |
| Core Voltage | 2.5 V | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL-2/3, LVDS | — |
| パッケージ | 652-ball PBGA (45 x 45 mm, 1.27 mm pitch) | 655-pin CPGA (Ceramic Pin Grid Array) |
| 実装タイプ | Surface Mount | Through-Hole |
| Programming Interface | IEEE 1149.1 JTAG | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status not stated in retrieved snippets] | Non-compliant (contains lead in ceramic package) |
| 動作温度 | Industrial (per datasheet) | 0 °C to +85 °C (commercial) |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 212,992 |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| Propagation Delay | — | 2.5 ns |
| ピン数 | — | 655 |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |