EP20K400FI672-3N vs EP20K400FI672-1N 比較
詳細な並列比較: EP20K400FI672-3N メーカー: Altera および EP20K400FI672-1N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K400FI672-3N | EP20K400FI672-1N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Unknown | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $171.00 |
| Device Type | CMOS loadable programmable logic device | — |
| Product Family | APEX 20K | — |
| Series | EP20K400 | — |
| Propagation Delay | 3.6 ns | — |
| 最大クロック周波数 | 833 MHz | — |
| User I/O Count | 502 | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | — |
| パッケージ | S-PBGA-B672 | FineLine BGA-672 (26x26 mm) |
| Terminal Count | 672 terminals | — |
| Terminal Pitch | 1.000 mm | — |
| 実装タイプ | Surface mount | Surface Mount |
| Logic Capacity | [DATA_NEEDED: logic capacity] | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| RoHS ステータス | unknown | Compliant (Pb-free, N suffix) |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Device | — | EP20K400 |
| Maximum System Gates | — | 1,052,032 |
| Typical Gates | — | 400,000 |
| Logic Elements | — | 16,640 |
| Embedded System Blocks (ESBs) | — | 104 |
| Maximum RAM Bits | — | 212,992 |
| PLLs | — | 4 |
| User I/O Pins | — | 502 |
| Total Terminals | — | 672 |
| Speed Grade | — | -1 (fastest) |
| Core Voltage | — | 2.5 V (2.375 V to 2.625 V) |
| MSLレベル | — | 3 |
| Peak Reflow Temperature | — | 220 C |