EP20K400GI655-3 vs EP20K400GC655-3V 比較
詳細な並列比較: EP20K400GI655-3 メーカー: Altera および EP20K400GC655-3V メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K400GI655-3 | EP20K400GC655-3V |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $55.00 | $160.00 |
| Family | APEX 20KE | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (maximum) | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | — |
| Number of Terminals | 655 | — |
| パッケージ | 655-Pin PGA (Plastic/CPGA, square) | 655-BCPGA (62.48 mm x 62.48 mm) |
| JESD-30 Code | S-CPGA-P655 | — |
| Package Shape | Square | — |
| Form of Terminal | PIN/PEG (through-hole) | — |
| 実装タイプ | Through-Hole (Socket) | Through Hole (CPGA) |
| Process Technology | CMOS, 2.5V core | CMOS |
| Core Supply Voltage | 2.5 V | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | — |
| 動作温度 | 0°C to 70°C (Industrial I grade) | [DATA_NEEDED: commercial / industrial / military grade] |
| Speed Grade | -3 (slowest of the EP20K400 family) | -3V (commercial temperature, Vcc 1.8 V) |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | — |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] |
| Series | — | APEX-20KC |
| Manufacturer | — | Altera (now Intel) |
| Logic Elements | — | 16640 |
| Total RAM Bits | — | 212992 |
| Typical Gate Count | — | 400000 |
| Number of User I/O | — | 496 |
| 最大クロック周波数 | — | 714.2 MHz |
| Propagation Delay | — | 3.6 ns |
| Package Equivalence Code | — | SPGA655, 47x47 |
| Peak Reflow Temperature | — | 220 C |
| Configuration | — | SRAM-based (requires EPC configuration device) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |