EP20K400GI655-3 vs EP20K400GI655-2X 比較
詳細な並列比較: EP20K400GI655-3 メーカー: Altera および EP20K400GI655-2X メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K400GI655-3 | EP20K400GI655-2X |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $55.00 | $195.00 |
| Family | APEX 20KE | APEX-20K (loadable PLD / FPGA) |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (maximum) | 400,000 |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 4 | — |
| Number of Terminals | 655 | — |
| パッケージ | 655-Pin PGA (Plastic/CPGA, square) | 655-ball FineLine BGA (SPGA655, 47x47 mm) |
| JESD-30 Code | S-CPGA-P655 | — |
| Package Shape | Square | — |
| Form of Terminal | PIN/PEG (through-hole) | — |
| 実装タイプ | Through-Hole (Socket) | — |
| Process Technology | CMOS, 2.5V core | CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | — |
| 動作温度 | 0°C to 70°C (Industrial I grade) | — |
| Speed Grade | -3 (slowest of the EP20K400 family) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | — |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Series | — | APEX-20K |
| Logic Elements (LEs) | — | 16,640 |
| Total I/O Lines | — | 496 (bidirectional) + 4 (dedicated inputs) |
| Embedded Memory (bits) | — | 212,992 |
| Nominal Core Supply Voltage | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| I/O Supply Voltages | — | 2.5 V / 3.3 V |
| Propagation Delay (typical, -2 grade) | — | 3.1 ns |
| Package Code | — | SPGA655, 47x47 |
| Surface Mount | — | Yes (BGA) |
| 湿気感度レベル（MSL） | — | 1 |
| Operating Temperature (industrial -X grade) | — | -40C to +85C (industrial) |
| Qualification | — | Not Qualified (per distributor listing) |
| JTAG Support | — | IEEE 1149.1 boundary-scan / programming |