EP20K600CB652I8 vs EP20K600CB652I7N 比較
詳細な並列比較: EP20K600CB652I8 メーカー: Intel および EP20K600CB652I7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K600CB652I8 | EP20K600CB652I7N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $92.00 | $158.00 |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K600 | — |
| System Gates | 600,000 | — |
| Logic Elements / Cells | 24,320 | — |
| Maximum Operating Frequency | 301.21 MHz | 375.94 MHz |
| Propagation Delay (tpd) | 1.78 ns (CMOS) | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | 1.8 V |
| 動作温度 | -40 °C to +85 °C (Industrial) | — |
| パッケージ | 652-ball FineLine BGA (S-PBGA-B652) | 652-pin FineLine BGA |
| Package Code | BGA, square | — |
| Ball Pitch | 1.27 mm | — |
| Package Body Size | 45 mm × 45 mm | — |
| User I/O Lines | 488 | — |
| Dedicated Clock Inputs | 4 | — |
| Programming Interface | IEEE 1149.1 JTAG (in-system) | — |
| 実装タイプ | Surface Mount | Surface Mount (BGA) |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | unknown |
| Typical Gates | — | 600,000 |
| Logic Elements (Cells) | — | 24,320 |
| User I/O Banks | — | [DATA_NEEDED: User I/O Banks] |
| Maximum User I/O | — | [DATA_NEEDED: Maximum User I/O] |
| Embedded System Block (ESB) Memory | — | 311,040 bits |
| Phase-Locked Loops (PLLs) | — | 4 |
| Operating Temperature Grade | — | Industrial (-40C to +100C) |
| Speed Grade | — | 7 |
| Configuration Method | — | SRAM-based, JTAG (IEEE 1149.1) |