EP20K600CF672C6 vs EP20K600CF672C7ES 比較
詳細な並列比較: EP20K600CF672C6 メーカー: Altera および EP20K600CF672C7ES メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K600CF672C6 | EP20K600CF672C7ES |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $480.00 | $360.00 |
| Family | APEX 20KC | APEX 20K |
| Typical Gate Count | 600,000 gates | — |
| Logic Elements (LEs) | 24,320 | — |
| Embedded System Blocks (ESBs) | 160 (each 2,048 bits) | — |
| Maximum Embedded RAM | 311,296 bits (311 kbit) | — |
| Maximum User I/O Pins | 508 | — |
| パッケージ | 672-ball FineLine BGA (CF672) | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | -6 (C6) | — |
| 動作温度 | 0 °C to +85 °C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Core Voltage | 1.8 V | — |
| I/O Standards Supported | LVCMOS, LVTTL, HSTL, SSTL, GTL+ | — |
| Embedded PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS, 6 metal layers | 0.15 µm CMOS |
| Configuration Method | SRAM-based, JTAG, EPC16/EPC2 | — |
| RoHS ステータス | Non-RoHS (legacy process) | [DATA_NEEDED: RoHS compliance] |
| Series | — | APEX 20KC |
| Logic Elements / Cells | — | 24320 |
| System Gates | — | 600000 |
| Maximum User I/O | — | 504 |
| Maximum Input Lines | — | 508 |
| Number of Macrocells | — | 504 |
| Maximum Operating Frequency | — | 375.94 MHz (per FPGAkey listing) |
| Propagation Delay | — | 1.6 ns |
| Internal Reference Clock | — | 1666.6 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| Package Type | — | FC-FBGA |
| Pin / Ball Count | — | 672 |
| Grade Suffix | — | ES (engineering sample / extended screening) |
| 実装タイプ | — | Surface Mount (BGA) |
| MSLレベル | — | [DATA_NEEDED: MSL rating] |
| Configuration Memory | — | SRAM-based (volatile) |