EP20K600CF672I7N vs EP20K600CF672I8 比較
詳細な並列比較: EP20K600CF672I7N メーカー: Intel および EP20K600CF672I8 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K600CF672I7N | EP20K600CF672I8 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $232.00 | $195.00 |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 µm CMOS | — |
| Maximum System Gates | 600,000 | — |
| Logic Elements | 24,320 | — |
| Maximum User I/O Pins | 508 | — |
| Maximum Internal Frequency | 376 MHz | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Total Embedded RAM (max) | 311,296 bits | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | — |
| パッケージ | 672-ball FineLine BGA (FC-FBGA) | — |
| Ball Pitch | 1.0 mm | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | I7 (-40 °C to +100 °C industrial) | — |
| Propagation Delay (typical) | 1.6 ns | 1.48 ns |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | — |
| Lead-Free Finish (N suffix) | Yes | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | Compliant per legacy product records |
| Device Type | — | SPLD / FPGA |
| Logic Elements / Cells | — | 24,320 |
| Macros (Logic Cells) | — | 2432 |
| Typical Gate Count | — | 600,000 gates |
| Embedded Memory | — | 311,296 bits |
| User I/Os | — | 488 to 508 |
| ピン数 | — | 652 (functional) / 672 (BGA balls) |
| Internal Frequency (max) | — | [DATA_NEEDED: max internal frequency in MHz] |
| Core Supply Voltage | — | 1.8 V |
| Process Technology | — | 0.15 µm all-layer copper |
| 動作温度 | — | 0 °C to +85 °C (Industrial) |
| Package Type | — | 672-ball BGA, 45 x 45 mm, 1.27 mm pitch |
| 実装タイプ | — | Surface Mount |
| Configuration Interface | — | JTAG / Passive Serial |
| Design Tool | — | Quartus II (legacy MAX+PLUS II) |