EP20K600EBC652-2X vs EP20K600EFC33-2X 比較
詳細な並列比較: EP20K600EBC652-2X メーカー: Altera および EP20K600EFC33-2X メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K600EBC652-2X | EP20K600EFC33-2X |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $275.00 | $815.00 |
| Device Family | APEX 20KE | — |
| Device Type | SPLD / FPGA (Field Programmable Gate Array) | — |
| Logic Elements (LEs) | 24,320 | — |
| Macros | 24,320 | — |
| Embedded Memory Bits | 311,296 bits | — |
| User I/Os | 488 | — |
| パッケージ | 652-ball BGA, 45 x 45 mm, 1.27 mm pitch | 1020-ball FC-FBGA (33 mm x 33 mm) |
| Total Pins / Balls | 652 | — |
| Propagation Delay | 1.48 ns | 1.48 ns |
| 動作温度 | 0 °C to +85 °C (commercial) | 0C to +85C |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 um all-layer copper metal |
| Core Supply Voltage | 2.5 V | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL, GTL+ | — |
| Configuration Modes | Passive serial, passive parallel, JTAG (IEEE 1149.1) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Non-compliant (legacy Altera product) |
| Series | — | APEX-20KE |
| Family | — | APEX 20K (System-on-a-Programmable-Chip) |
| Logic Elements / Cells | — | 24320 |
| Total Gates | — | 600000 |
| Total RAM Bits | — | 311296 |
| Number of I/O | — | 588 |
| Maximum Internal Frequency | — | 200 MHz |
| Ball Pitch | — | 1.27 mm |
| Lead-Free Status | — | Contains lead (legacy) |
| Multi-Voltage I/O Support | — | 1.5V / 1.8V / 2.5V / 3.3V / 5.0V |
| Embedded System Blocks | — | Dual-port RAM / FIFO configurable |