EP20K600EBC652-2X vs EP20K600EFC672-2X 比較
詳細な並列比較: EP20K600EBC652-2X メーカー: Altera および EP20K600EFC672-2X メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K600EBC652-2X | EP20K600EFC672-2X |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $275.00 | $115.00 |
| Device Family | APEX 20KE | — |
| Device Type | SPLD / FPGA (Field Programmable Gate Array) | — |
| Logic Elements (LEs) | 24,320 | — |
| Macros | 24,320 | — |
| Embedded Memory Bits | 311,296 bits | 311,296 |
| User I/Os | 488 | — |
| パッケージ | 652-ball BGA, 45 x 45 mm, 1.27 mm pitch | — |
| Total Pins / Balls | 652 | — |
| Propagation Delay | 1.48 ns | — |
| 動作温度 | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL, GTL+ | — |
| Configuration Modes | Passive serial, passive parallel, JTAG (IEEE 1149.1) | — |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Not RoHS compliant (X suffix is SnPb); use -2N suffix for lead-free |
| Family | — | APEX 20KE |
| Typical Gates | — | 600,000 |
| Logic Elements / Cells | — | 24,320 |
| Maximum User I/O | — | 508 |
| Number of PLLs | — | 4 |
| Package Type | — | 672-pin FineLine BGA (FC-FBGA) |
| Package Size | — | 45 x 45 mm, 1.27 mm pitch |
| Core Voltage | — | 1.8 V |
| Propagation Delay (typical) | — | 1.48 ns |
| Maximum Internal Frequency | — | 200 MHz |
| Lead-Free Variant | — | EP20K600EFC672-2N |
| Configuration Method | — | Serial / Parallel (Quartus-supported) |