EP20K60ETC144-1X vs EP20K60EFC144-2XN 比較
詳細な並列比較: EP20K60ETC144-1X メーカー: Intel および EP20K60EFC144-2XN メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EP20K60ETC144-1X - 60K-Gate APEX-20KE FPGA, 144-LQFP | Intel/Altera
EP20K60ETC144-1X ⚠ ラストタイムバイAltera
EP20K60EFC144-2XN - APEX-20KE FPGA 60K Gates 93 I/O 144-BGA | Intel/Altera
EP20K60EFC144-2XN Nrnd仕様比較
| パラメータ | EP20K60ETC144-1X | EP20K60EFC144-2XN |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $152.00 | $152.00 |
| Series | APEX-20KE | APEX-20KE |
| Logic Elements / Cells | 2,560 | — |
| Total Gates | 60,000 | — |
| Total RAM Bits | 32,768 | — |
| Number of I/O | 92 | — |
| Number of Logic Elements/Cells | 2,560 | — |
| Core Voltage | 1.8 V (1.71 V to 1.89 V) | — |
| Propagation Delay | 1.72 ns | — |
| Internal Frequency (Max) | 160 MHz | — |
| 動作温度 | 0 C to +85 C | — |
| Process Technology | 0.22 um CMOS | — |
| パッケージ / ケース | 144-LQFP | — |
| Supplier Device Package | 144-TQFP (20x20 mm) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| Terminal Pitch | 0.5 mm | — |
| Lead Finish / Terminal Form | Gull Wing (LQFP) | — |
| Logic Family | CMOS | CMOS, SRAM-based LUT |
| Architecture | MultiCore (SOPC) | — |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Family | — | APEX-20K (MultiCore Architecture) |
| Typical Gate Count | — | 60,000 gates |
| Logic Elements / Embedded Array Blocks | — | 2,560 |
| Embedded Memory (Bits) | — | 32,768 |
| Maximum User I/O | — | 93 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO range] |
| Package Type | — | 144-BGA (Fine-pitch Ball Grid Array) |
| Package Code (per MPN suffix) | — | FBGA / LBGA, 13x13 mm |
| Operating Temperature (TJ) | — | 0 C to +85 C (commercial) |
| Speed Grade | — | -2 (per MPN suffix) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Parallel |