EP2A40F1020I9N vs EP2A40F1020C8N 比較
詳細な並列比較: EP2A40F1020I9N メーカー: Intel および EP2A40F1020C8N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2A40F1020I9N | EP2A40F1020C8N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $165.00 | $0.00 |
| Family | APEX II | — |
| Device Logic Elements / Cells | 38,400 cells | — |
| System Gates | 1,500,000 (1.5 M) | — |
| Maximum Operating Frequency | 366 MHz | — |
| Process Technology | 0.15 um CMOS, up to 8 metal layers | — |
| Core Supply Voltage | 1.5 V | — |
| User I/O Count | 735 bidirectional I/O | — |
| パッケージ | 1020-pin FC-FBGA (Flip-Chip FineLine BGA) | — |
| Operating Temperature Grade | Industrial (I9 suffix: -40C to +100C per Altera APEX II convention) | — |
| High-Speed I/O Standards | True-LVDS (up to 1 Gbps), LVPECL, PCML, HyperTransport | — |
| Embedded Memory | ESB-based True-Dual-Port/Single-Port RAM, ROM, CAM (bits [DATA_NEEDED: total RAM bits]) | — |
| Clock Management | PLLs (count [DATA_NEEDED: PLL count]) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous/Synchronous, JTAG | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | unknown |
| ライフサイクル状態 | Obsolete (per distributor listings / Altera APEX II family EOL) | — |
| Product Type | — | Field-Programmable Gate Array (FPGA) |
| Device Family | — | APEX II |
| Logic Technology | — | CMOS |
| Logic Gates | — | 1.5 million |
| Logic Cells | — | 38,400 |
| Nominal Supply Voltage | — | 1.5 V |
| Supply Voltage Range | — | 1.425 V to 1.575 V |
| User I/Os | — | 735 |
| Package Terminal Count | — | 1,020 pins |
| Package Type | — | FC-FBGA, BGA-1020 |
| Package Body Size | — | 33 mm x 33 mm |
| Ball Pitch | — | 1 mm |
| Reported Operating Frequency | — | 376 MHz |
| Alternative Reported Frequency | — | 562 MHz |
| Reported Propagation Delay | — | 1.78 ns |
| Alternative Reported Propagation Delay | — | 1.55 ns |
| Fabrication Process | — | 0.15 µm |
| Maximum Reported Metal Layers | — | 8 layers |
| 動作温度 | — | 0 °C to 85 °C |
| Terminal Form | — | Ball |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | unknown |