EP2C35F672C8 vs EP2C50F672C7 比較
詳細な並列比較: EP2C35F672C8 メーカー: Altera および EP2C50F672C7 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2C35F672C8 | EP2C50F672C7 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $71.85 | $184.59 |
| Family | Cyclone II | Cyclone II |
| Logic Elements (LEs) | 33,216 | — |
| Total RAM Bits | 483,840 | — |
| Embedded Multipliers (18x18) | 35 | — |
| User I/O Pins (max) | 475 | — |
| Number of PLLs | 4 | — |
| パッケージ | 672-BGA (FineLine BGA, 1.0 mm pitch) | 672-ball FineLine BGA (FBGA-672) |
| Speed Grade | C8 (commercial, 8 ns pin-to-pin) | -7 |
| Process Technology | 90 nm | 90 nm CMOS with low-k dielectric |
| Core Voltage (VCCINT) | 1.15 V - 1.25 V | 1.2 V |
| Operating Temperature (Commercial) | 0C to +85C | — |
| Configuration Modes | Active Serial (AS), Passive Serial (PS), JTAG | Passive Serial (PS), Active Serial (AS), JTAG |
| Memory Interface Support | DDR, DDR2, SDR SDRAM | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, LVDS, RSDS, mini-LVDS, PPDS | — |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | Compliant (lead-free package) | — |
| Logic Elements (LE) | — | 50,528 |
| Embedded Memory Bits | — | 594,432 bits |
| Embedded Memory Blocks | — | 250 M4K blocks (4 Kbit each) |
| Embedded 18x18 Multipliers | — | 86 (150 per device family datasheet figure) |
| User I/O Pins | — | 450 |
| Phase-Locked Loops (PLL) | — | 4 |
| Global Clock Networks | — | 16 |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V (per bank) |
| Temperature Grade | — | Commercial (0C to +85C junction) |
| Lead-Free / RoHS | — | Lead-Free / RoHS compliant per Heisener listing |