EP2S130F1020C5N vs EP2S130F1020C5ES 比較
詳細な並列比較: EP2S130F1020C5N メーカー: Intel および EP2S130F1020C5ES メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP2S130F1020C5N | EP2S130F1020C5ES |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1,320.00 | $1,380.00 |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Adaptive Logic Modules (ALMs) | 6627 LABs (per Jotrin listing) | 53,016 |
| Total Memory Bits | 6,747,840 bits | — |
| User I/Os | 734 | — |
| Process Technology | 90 nm | 90 nm |
| Core Supply Voltage (VCCINT) | 1.15 V to 1.25 V | — |
| Maximum Internal Frequency | 609.76 MHz | — |
| パッケージ | 1020-ball FC-FBGA (33x33 mm) | 1020-ball FC-FBGA (flip-chip BGA) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | Commercial (0C to +85C, C5 grade) | — |
| Temperature Grade | C5 (other - per Partstack) | — |
| RoHS ステータス | [DATA_NEEDED: rohs status] | Compliant (lead-free) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| PLLs | 4 (typical Stratix II feature) | [DATA_NEEDED: PLL count] |
| Global Clock Networks | 16 (typical Stratix II feature) | — |
| Configuration Method | Serial/Parallel via Quartus II (typical Stratix II) | — |
| Country of Origin | Republic of Korea (per GlobalSpec) | — |
| ECCN | 3A001.a.7.a (per GlobalSpec) | — |
| Estimated EOL Date | 2023 (per GlobalSpec) | — |
| Embedded Memory Bits | — | 6,747,840 |
| Maximum User I/Os | — | 742 |
| Core Voltage | — | 1.2 V |
| Maximum Internal Clock Frequency | — | 609.76 MHz |
| Speed Grade | — | -5 |
| Operating Temperature (Junction) | — | 0C to 85C (commercial) |
| Logic Array Blocks (LABs) | — | 6,747 |
| Total RAM Blocks | — | [DATA_NEEDED: total RAM blocks] |
| Embedded DSP Blocks | — | [DATA_NEEDED: embedded DSP blocks count] |
| Embedded 18x18 Multipliers | — | [DATA_NEEDED: 18x18 multiplier count] |
| Configuration | — | SRAM-based, JTAG/AS/PS modes |