EP2S180F1508C4TT vs EP2S180F1508C3NAA 比較
詳細な並列比較: EP2S180F1508C4TT メーカー: Altera および EP2S180F1508C3NAA メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EP2S180F1508C4TT - 180K Logic Elements FPGA | Altera | High-Performance Digital Logic
EP2S180F1508C4TT Obsolete
仕様比較
| パラメータ | EP2S180F1508C4TT | EP2S180F1508C3NAA |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $285.00 |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | Stratix II | — |
| Logic Elements | approximately 180,000 | 179,400 LEs |
| User I/O | 1,170 pins | — |
| Logic Array Blocks | 8,970 LABs | — |
| パッケージ | 1,508-ball FBGA | 1508-ball FCBGA |
| 実装タイプ | Surface Mount | Surface Mount |
| Temperature Grade | -T | — |
| Configuration Mechanism | [DATA_NEEDED: configuration mechanism] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Core Voltage | [DATA_NEEDED: core voltage] | [DATA_NEEDED: VCCINT nominal] |
| I/O Voltage | [DATA_NEEDED: I/O voltage] | — |
| 動作温度 | [DATA_NEEDED: operating temperature] | [DATA_NEEDED: operating temperature grade] |
| Storage Temperature | [DATA_NEEDED: storage temperature] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Ball Pitch | [DATA_NEEDED: ball pitch] | — |
| Typical Power Dissipation | [DATA_NEEDED: typical power dissipation] | — |
| RoHS ステータス | unknown | unknown |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Family | — | Stratix II |
| Adaptive Logic Modules (ALMs) | — | 71,760 ALMs |
| Embedded RAM (total) | — | 9,383,040 bits (M4K + M-RAM) |
| M4K RAM Blocks | — | 930 blocks of 4 Kbits each |
| M-RAM Blocks | — | 9 blocks of 512 Kbits each |
| DSP Blocks | — | 96 blocks (18x18 multipliers) |
| 18x18 Embedded Multipliers | — | 384 |
| Transceivers | — | 12 channels |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| Maximum User I/O | — | 1170 user I/O pins |
| Process Technology | — | 90 nm CMOS |
| Speed Grade | — | -3 (commercial, faster) |