EP2S180F1508C4TT vs EP2S180F1508C5 比較
詳細な並列比較: EP2S180F1508C4TT メーカー: Altera および EP2S180F1508C5 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EP2S180F1508C4TT - 180K Logic Elements FPGA | Altera | High-Performance Digital Logic
EP2S180F1508C4TT ObsoleteAltera
EP2S180F1508C5 - 179K LEs Stratix II FPGA, 1170 I/O, 1508-FBGA | Altera
EP2S180F1508C5 ⚠ ラストタイムバイ仕様比較
| パラメータ | EP2S180F1508C4TT | EP2S180F1508C5 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $4,880.00 |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | Stratix II | — |
| Logic Elements | approximately 180,000 | 179,400 |
| User I/O | 1,170 pins | — |
| Logic Array Blocks | 8,970 LABs | — |
| パッケージ | 1,508-ball FBGA | 1508-FBGA (FCBGA), 40 mm × 40 mm |
| 実装タイプ | Surface Mount | Surface Mount |
| Temperature Grade | -T | — |
| Configuration Mechanism | [DATA_NEEDED: configuration mechanism] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Core Voltage | [DATA_NEEDED: core voltage] | 1.15 V to 1.25 V |
| I/O Voltage | [DATA_NEEDED: I/O voltage] | — |
| 動作温度 | [DATA_NEEDED: operating temperature] | 0 °C to 85 °C (commercial, C5 speed grade) |
| Storage Temperature | [DATA_NEEDED: storage temperature] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Ball Pitch | [DATA_NEEDED: ball pitch] | — |
| Typical Power Dissipation | [DATA_NEEDED: typical power dissipation] | — |
| RoHS ステータス | unknown | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Family | — | Stratix II |
| Series | — | EP2S180 |
| Equivalent LEs | — | ~179,400 |
| Logic Array Blocks (LABs) | — | 8,970 |
| Adaptive Logic Modules (ALMs) | — | 71,760 |
| Total RAM Bits | — | 9,383,040 |
| Embedded Memory | — | M512 / M4K / M-RAM blocks |
| DSP Blocks | — | 96 |
| User I/O Pins | — | 1,170 |
| Maximum User I/O | — | 1,170 |
| Process Technology | — | 90 nm, all-layer copper, SRAM |
| Speed Grade | — | C5 |
| Configuration | — | SRAM, JTAG / Passive Serial / Fast Passive Parallel / Active Serial |