EP2S60F484I5N vs EP2S60F484C4N 比較

詳細な並列比較: EP2S60F484I5N メーカー: Altera および EP2S60F484C4N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP2S60F484I5N EP2S60F484C4N
ブランド Altera Intel
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $1,325.00 $920.00
Series Stratix II (EP2S60) Stratix II
Family Field Programmable Gate Array (FPGA) Stratix II FPGA
Logic Elements (LE) 60,440 60,440
Adaptive Logic Modules (ALM) 24,176 30,220
Embedded Memory (bits) 2,544,192 —
Embedded Memory (M512/M4K/M-RAM blocks) M512: 330, M4K: 255, M-RAM: 2 —
DSP Blocks (18-bit multipliers) 48 blocks (192 18x18 multipliers) —
PLLs 12 (4 enhanced + 8 fast) Up to 12
Maximum User I/O Pins 334 —
Maximum Fabric Clock 609.76 MHz —
Core Supply Voltage 1.2 V typical 1.2 V
Process Technology 90 nm CMOS 90 nm CMOS
パッケージ 484-ball FC-FBGA (Flip-Chip Fine-pitch BGA), 1.00 mm pitch 484-Ball FBGA (FineLine BGA)
Speed Grade I5 (industrial, slow-speed for low power) —
動作温度範囲 -40 °C to +100 °C (industrial) —
実装タイプ Surface Mount (BGA) Surface Mount
RoHS ステータス [DATA_NEEDED: rohs status not stated in verified data] [DATA_NEEDED: RoHS Status]
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free / halogen-free status] —
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel —
Design Tool Quartus II (legacy; current Intel Quartus Prime with Stratix II device support) —
Embedded Memory (Bits) — 2,544,192
DSP Blocks (18x18 Multipliers) — 36
Maximum User I/O — 334
User I/O Banks — [DATA_NEEDED: User I/O Banks]
Maximum Internal Clock Frequency — 711.24 MHz
Operating Temperature Grade — Commercial (C4)
Configuration Modes — Passive Serial, Fast Passive Parallel, JTAG
Lead-Free — [DATA_NEEDED: Lead-Free]

データシート&リソース

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