EP2SGX130GF40C4NES vs EP2SGX130GF40C4ES 比較

詳細な並列比較: EP2SGX130GF40C4NES メーカー: Intel および EP2SGX130GF40C4ES メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

Intel
EP2SGX130GF40C4NES EP2SGX130GF40C4NES - 132K LE Stratix II GX FPGA, 6.375Gbps SERDES, 1508-FBGA | Intel

EP2SGX130GF40C4NES - 132K LE Stratix II GX FPGA, 6.375Gbps SERDES, 1508-FBGA | Intel

EP2SGX130GF40C4NES ⚠ ラストタイムバイ

仕様比較

パラメータ EP2SGX130GF40C4NES EP2SGX130GF40C4ES
ブランド Intel Intel
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 ラストバイ Unknown
在庫状況 In Stock In Stock
単価(USD) $1,380.00 $0.00
Family Stratix II GX —
Logic Elements 132,540 —
Logic Blocks / ALMs Approximately 53,000 ALMs —
Process Technology 90 nm CMOS —
Core Voltage 1.2 V —
Maximum Transceiver Data Rate 6.375 Gbps —
Transceiver Channels Up to 20 (4 to 20, device-dependent) —
User I/O Pins 734 —
Total Package Pins 1508 (FC-FBGA ball grid) —
Package Code GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch) —
Speed Grade C4 (speed grade -4) —
Internal Operating Frequency Up to 717 MHz —
Embedded Memory Approximately 4.5 Mbits (TriMatrix) —
PLL Blocks 8 —
DSP Blocks Yes (variable, see datasheet) —
実装タイプ Surface Mount (flip-chip BGA) Surface mount
Lead-Free / RoHS Yes (LEAD FREE per datasheet family code) —
MSLレベル Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level] —
動作温度 Commercial Extended (per N suffix) —
JEDEC Standard Reference MS-034AAU-1 —
Product Type — Field-programmable gate array (FPGA)
Product Family — Stratix II GX
Logic Cells — 132,540
Configurable Logic Blocks — 7,047 CLBs
Logic Technology — CMOS
User I/O — 734 I/O
Internal Frequency — 717 MHz
Supply Voltage Range — 1.15 V to 1.25 V
Package Pin Count — 1,508 pins
Package Type — FBGA-1508
Package Body Size — 40 mm by 40 mm
Ball Pitch — 1 mm
Package Designation — MS-034AAU-1
Lead-Free — Yes
動作温度範囲 — [DATA_NEEDED: operating temperature range]
Transceiver Count — [DATA_NEEDED: transceiver count]
Configuration Memory Type — [DATA_NEEDED: configuration memory type]

データシート&リソース

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