EP3SE50F484C2G vs EP3SL50F484C2G 比較
詳細な並列比較: EP3SE50F484C2G メーカー: Intel および EP3SL50F484C2G メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP3SE50F484C2G | EP3SL50F484C2G |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1,180.00 | $335.00 |
| Series | Stratix III E | — |
| Number of Logic Elements / Cells | 47,500 | — |
| Number of LABs / CLBs | 1,900 | — |
| Total RAM Bits | 5,760,000 (5,760 Kbit) | — |
| Number of User I/O | 296 | — |
| パッケージ / ケース | 484-BBGA, FCBGA (FineLine BGA) | — |
| 実装タイプ | Surface Mount | — |
| Core Voltage Supply | 0.86 V to 1.15 V | — |
| 動作温度 | 0 °C to +85 °C (TJ) | — |
| Process Technology | 40 nm TSMC low-power CMOS | 65 nm CMOS |
| Logic Element Architecture | Adaptive Logic Module (ALM) with 8-input fracturable LUT | — |
| Embedded DSP Blocks | Yes (variable-precision multipliers) | — |
| Transceivers | Multi-gigabit transceivers (selected package pins) | — |
| Memory Interface Support | DDR / DDR2 / DDR3 with hard PHY | — |
| Partial Reconfiguration | Supported | — |
| Configuration Interface | JTAG, Passive Serial, Fast Passive Parallel | — |
| Part Status | Active (Intel catalogue); long-term supply subject to Stratix III lifecycle policy | — |
| RoHS ステータス | Compliant | Compliant |
| Family | — | Stratix III L |
| Logic Elements | — | 47,500 LE |
| Adaptive Logic Modules (ALMs) | — | 19,000 ALM |
| Embedded Memory | — | 2,184,192 bits (2.08 Mbit) |
| Maximum User I/Os | — | 296 I/O |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| Operating Supply Voltage (Core) | — | 1.1 V |
| Maximum Operating Temperature | — | +85 C |
| Minimum Operating Temperature | — | 0 C |
| 最大クロック周波数 | — | 600 MHz |
| パッケージ | — | 484-ball FCBGA (FBGA-484) |
| 実装スタイル | — | SMD/SMT |
| Packaging | — | Tray |
| Total Transceivers | — | [DATA_NEEDED: transceiver count] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |