EP3SL50F484C4L vs EP3SL50F484I4L 比較
詳細な並列比較: EP3SL50F484C4L メーカー: Intel および EP3SL50F484I4L メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP3SL50F484C4L | EP3SL50F484I4L |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obs | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $651.25 | $658.26 |
| Family | Stratix III L | Stratix III |
| Logic Elements (LE) | 47,500 | 47,500 |
| Logic Array Blocks (LABs) | 1,900 | — |
| User I/O Count | 296 | — |
| Total RAM Bits | 2,184,192 | — |
| Core Voltage | 0.9 V | — |
| Process Technology | 65 nm CMOS | 65 nm low-power CMOS |
| 動作温度範囲 | 0°C to 85°C (commercial) | — |
| パッケージ | 484-ball FBGA (FineLine BGA) | 484-ball FBGA (FCBGA) |
| 実装タイプ | Surface Mount | Surface Mount |
| Maximum Fabric Frequency | [DATA_NEEDED: maximum fabric frequency] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | Family supports up to 384 18x18 multipliers (family-level) |
| Transceivers | [DATA_NEEDED: number of transceivers] | Family supports up to 4 transceivers per family datasheet |
| MSLレベル | 3 (per JEDEC J-STD-020) | — |
| RoHS ステータス | Compliant | — |
| Design Software | Quartus II | — |
| Architecture | Adaptive Logic Module (ALM) | — |
| Series | — | Stratix III L (Low Power) |
| Embedded Memory Bits | — | 2,184,192 bits (~273 KB) |
| User I/O Pins | — | 296 |
| Speed Grade | — | 4 |
| 動作温度 | — | 0 °C to 85 °C (commercial, per DigiKey listing) |
| 電源電圧 | — | 0.9 V core (family-typical) |
| Lead-Free / RoHS | — | Yes (RoHS compliant) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |