EP3SL50F484I3N vs EP3SL50F484I4LN 比較
詳細な並列比較: EP3SL50F484I3N メーカー: Intel および EP3SL50F484I4LN メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP3SL50F484I3N | EP3SL50F484I4LN |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | ラストバイ | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $552.30 | $0.00 |
| Family | Stratix III L | — |
| Logic Elements | 47,500 | — |
| Logic Array Blocks (LABs) | 1,900 | — |
| Embedded Memory | 2,184,192 bits (2.1 Mbit) | 2,184,192 bits |
| Embedded 18x18 Multipliers | 218 | — |
| Maximum User I/O | 296 | — |
| Process Technology | 65 nm CMOS | CMOS |
| Core Voltage | 0.9 V / 1.1 V | [DATA_NEEDED: core voltage] |
| Maximum Core Frequency | 500 MHz | — |
| パッケージ | 484-ball FBGA (FC-FBGA, 23x23 mm, 1.0 mm pitch) | 484-BBGA, FCBGA |
| 動作接合温度 | -40C to +100C (Industrial) | — |
| 実装タイプ | Surface Mount (SMT) | — |
| Lead-Free / RoHS | Lead Free / Compliant | — |
| MSLレベル | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | — |
| Programming Tool | Quartus II (legacy) | — |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Device Family | — | Stratix III L |
| Logic Cells | — | 47,500 |
| User I/O | — | 296 |
| Logic Array Blocks | — | 1,900 LABs |
| Listed Frequency | — | 717 MHz |
| Package Description | — | FBGA-484 |
| Terminal Count | — | 484 |
| Terminal Form | — | Ball |
| Package Body Material | — | Plastic/Epoxy |
| Lead-Free Status | — | Lead free |
| Operating Temperature Grade | — | Industrial |
| I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |
| I/O Voltage | — | [DATA_NEEDED: I/O voltage] |
| Junction Temperature | — | [DATA_NEEDED: junction temperature] |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status] |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |